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preliminary rev. 0.81 6/06 copyright ? 200 6 by silicon labora tories SI2107/08/09/10 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI2107/08/09/10 s atellite r eceiver for dvb-s/dss with q uick l ock and q uick s can features applications description the SI2107/08/09/10 are a fam ily of pin-compatible, complete front-end solutions for dss and dvb-s digital satellite recepti on. the ic family in corporates a tuner, demodulator, and lnb controller into a single device resulting in significantly reduced board space and external com ponent count. the device supports symbol rates of 1 to 45 mbaud over a 950 to 2150 mhz range. a full suite of features including automatic acquisition, fade recovery, blind scanning, performance monitoring, and diseqc level 2.2 compliant signaling are supported. the si2108/ 10 further add short circuit protection, overcurrent protection, and a step-up dc-dc controller to implement a low-cost lnb supply solution. si2109/10 versions include a hardware channel scan accelerator for fast ?blindscan?. the SI2107/08/ 09/10 family features new channel det ection and acquisition technology: quicklock for SI2107/08/09/10 and quickscan for si2109/10. quicklock achieves fast channel acquisition and quickscan , fast channel detection. an i 2 c bus interface is used to configure and monitor all internal parameters. functional block diagram single-chip tuner, demodulator, and lnb controller dvb-s- and dss-compliant qpsk/bpsk demodulation integrated step-up dc-dc converter for lnb power supply (si2108/10 only) input signal level: ?82 to ?10 dbm symbol rate range: 1 to 45 mbaud automatic acquisition and fade recovery automatic gain control on-chip blind scan accelerator with quickscan (si2109/10 only) diseqc? 2.2 support power, c/n, and ber estimators i 2 c bus interface 3.3/1.8 v supply, 3.3 v i/o pb-free/rohs-compliant package set-top boxes digital video recorders digital televisions satellite pc-tv smatv trans-modulators (satellite master antenna tv) acquisition control agc tuner a/d converter demodulator viterbi decoder de-interleaver rs decoder descrambler mpeg-ts lnb control rf sythesizer i 2 c interface xout scl sda int/rlk/gpo ts_err ts_sync ts_val ts_data[7:0] ts_clk pwm/dcs isen/nc lnb2/drc vsen/tdet rfip lnb1/tgen pin assignments SI2107/08/09/10 14 15 16 17 18 19 20 21 22 36 37 38 39 40 41 42 43 44 vdd_synth vdd_lo gnd rfip1 rfin1 rfin2 rfip2 vdd_lna rext addr vdd_mix vdd_bb vdd_adc vsen/tdet lnb1/tgen isen pwm/dcs vdd_dig18 ts_data[1] ts_data[7] ts_clk scl sda ts_sync ts_val ts_err int/rlk/gpo vdd_pll33 xtout vdd_xtal xtal2 xtal1 reset lnb2/drc ts_data[0] ts_data[3] ts_data[2] ts_data[4] ts_data[5] ts_data[6] vdd_dig33 vdd_dig33 gnd gnd top view 1 2 3 4 5 6 7 8 9 10 11 12 13 23 24 25 26 27 28 29 30 31 32 33 34 35 gnd gnd www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 2 preliminary rev. 0.81 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schemati cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. part versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1. tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3. dvb-s/dss channel decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4. on-chip blindscan controller: quickscan (si2109/10 only) . . . . . . . . . . . . . . . . . . 21 5.5. lnb signaling controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6. on-chip lnb dc-dc st ep-up controller (si2108/ 10 only) . . . . . . . . . . . . . . . . . . . 21 5.7. crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.1. system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3. receiver status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 6.4. tuning control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5. channel decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6. automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7. lnb signaling controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8. on-chip lnb dc-dc st ep-up controller (si2108/ 10 only) . . . . . . . . . . . . . . . . . . . 32 6.9. on-chip blindscan controller: quickscan (si2109/10 only) . . . . . . . . . . . . . . . . . . 32 7. i 2 c control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 8. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 9. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10. ordering guide1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11. package outline: 44-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 12. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 4 preliminary rev. 0.81 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit ambient temperature t a 0?70c dc supply voltage, 3.3 v v 3.3 3.0 3.3 3.6 v dc supply voltage, 1.8 v v 1.8 1.71 1.8 1.89 v note: all minimum and maximum specificati ons are guaranteed and apply across th e recommended operating conditions. table 2. absolute maximum ratings 1, 2 parameter symbol min max unit dc supply voltage, 3.3 v v 3.3 ?0.3 3.9 v dc supply voltage, 1.8 v v 1.8 ?0.3 2.19 v input voltage (pins 2, 3, 7, 9, 11_ v in ?0.3 v 3.3 + 0.3 v input current (pins 2, 3, 7, 9, 11) i in ?10 +10 ma operating ambient temperature t op ?10 +70 c storage temperature t stg ?55 150 c rf input level ? 10 dbm esd protection (pins 1?44) ? 2 kv notes: 1. permanent damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operations se ctions of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect device reliability. 2. the SI2107/08/09/10 is a high-performance rf integrated circuit. handling and assembly of these devices should only be done at esd-protected workstations. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 5 table 3. dc characteristics (v 3.3 = 3.3 v 10%, v 1.8 = 1.8 v 10%, t a =0?70oc) parameter symbol test condition min typ max unit supply current, 3.3 v i 3.3 45 mbaud, cr 7/8 1 ?313 ? ma 20 mbaud, cr 2/3 1 ?298 ? ma supply current, 1.8 v i 1.8 45 mbaud, cr 7/8 1 ?292 ? ma 20 mbaud, cr 2/3 1 ?217 ? ma input high voltage v ih scl(25), sda(26) 2.3 ? 5.5 v input low voltage v il scl(25), sda(26) 0 ? 0.8 v input leakage 2 i i scl(25), sda(26), reset(11), xtal1(35), vsen/ tdet(7) ?? 10 a output high voltage v oh 2.4 ? ? v output low voltage v ol ?? 0.4 v output leakage i ol ?? 10 a notes: 1. lnb dc-dc converter disabled; lnb_en (ceh[2]) = 0. 2. isen(9) is not tested for leakage current. table 4. rf electrical characteristics parameter symbol test condition min typ max unit input power, single channel p i,ch ??82 1 ?10 dbm aggregate input power p i,agg ? ? ?7 dbm input impedance, balanced z in z source =75 ? ?75 ? ? return loss ? ?10 ? db dynamic voltage gain range ? gv ?75 ? db maximum voltage gain g v(max) ?55 ? db noise figure nf max gain 2 ? +9.5 +12.5 db ip3 ip3 3 min gain 2 +5 +15 ? dbm lo leakage l lo 950 to 2150 mhz ? ? ?70 dbm lo ssb phase noise n lo 100 khz offset ? ?97 ?94 dbc/hz 1 mhz offset ? ?97 ?94 dbc/hz lo dsb phase noise (integrated) n lo 10 khz to 1/2 baud rate ?2.1 2.8 rms rf synthesizer spurious at 20 mhz offset ? ?40 ? dbc/hz lo oscillator settling time t s,lo ?100 ? s notes: 1. for a single channel with sr = 27.5 mbaud, cr = 7/8, and no added noise. input power range over which bit error rate is less than 2e-4 after viterbi decoder. 2. max gain = 0hffff in agc settings registers (25h?26h). min gain = 0h0000 in agc settings registers (25h?26h). 3. im3 can be calculated as follows: im3 = 2 x (ip3 ? p in ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 6 preliminary rev. 0.81 table 5. receiver characteristics parameter symbol test condition min typ max unit rf input frequency range f in 950 ? 2150 mhz fine tune step size f step ? 12.2 ? khz symbol rate range r s 1?45mbaud carrier offset correction range f car_off ? 6?mhz carrier lock/acquisition times with quicklock t ql 45 mbaud, cr = 7/8 channel offset = 5 mhz* ?0.02? sec 27.5 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.03? sec 20 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.04? sec 10 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.05? sec 5 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.08? sec 2 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.14? sec 1 mbaud, cr = 7/8, channel offset = 10 mhz* ?0.25? sec *note: for signal with c/n = 8.5 db pin = ?40 dbm, channel frequency = 1560 mhz. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 7 table 6. lnb supply characteristics (si2108/10 only) parameter symbol test condition min typ max unit supply voltage v lnb_in 81213.2v converter switch frequency 237 264 290 khz output high voltage vhigh = 1101 17.75 18.625 19.5 v vhigh = 1000 17.0 18.0 19.0 v output low voltage vlow = 1101 12.75 13.375 14.0 v vlow = 1100 12.5 13.25 14.0 v low to high transition time 13 to 18 v ? ? 1 ms high to low transition time 18 to 13 v ? ? 1 ms line regulation v cc =8 to 13.2 v i o =500ma ??200 ? mv load regulation i o =50 to 500 ma v cc =12v ??200 ? mv load capacitance tolerance diseqc 1.x ? ? 0.75 f diseqc 2.x ? ? 0.25 f output current limiting ilim = 00 400 ? 550 ma ilim = 01 500 ? 650 ma maximum lnb supply current imax = 01 1.4 1.6 1.92 a tone frequency f tone 20 22 24 khz tone amplitude 500 650 800 mv tone duty cycle 40 50 60 % tone rise and fall time 3 6 10 s tone detector frequency capture range 17.6 ? 26.4 khz tone detector input amplitude 200 ? 1000 mv pp note: specifications based on recommended schematics in figure 8 and figure 9. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 8 preliminary rev. 0.81 figure 1. i 2 c timing diagram table 7. i 2 c bus characteristics parameter symbol test condition min typ max unit scl clock frequency f scl 0 ? 400 khz bus free time between start and stop condition t buf 1.3 ? ? s hold time (repeated) start condition. (after this period, the first clock pulse is generated.) t hd, sta 0.6 ? ? s low period of scl clock t low 1.3 ? ? s high period of scl clock t high 0.6 ? ? s data setup time t su, dat 100 ? ? ns data hold time t hd, dat 0?0.9s scl and sda rise and fall time t r, t f ? ? 300 ns setup time for a repeated start con- dition t su, sta 0.6 ? ? s setup time for stop condition t su,sto 0.6 ? ? s capacitive load for each bus line c b ? ? 400 pf sda scl t f s t low t hd;sta t r t high t su;dat t f t hd;dat t su;sta s r t sp t hd;sta t su;sto t buf t r ps www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 9 figure 2. mpeg-ts (rising launch and capture) timing diagram table 8. mpeg-ts specifications (rising launch and capture) parameter symbol test condition min typ max unit clock cycle time t cycle serial mode 11.3 ? 28.6 ns parallel mode 77 ? 8000 ns clock low time t clow serial mode (tsscr = 11) 5.1 ? 6.9 ns serial mode (tsscr = 00) 12.0 ? 15.8 ns parallel mode 39 ? 4000 ns clock high time t chigh serial mode (tsscr = 01) 5.1 ? 6.9 ns serial mode (tsscr = 11) 12.0 ? 15.8 ns parallel mode 39 ? 4000 ns hold time t hold normal operation ? 0 ? ns data delayed (tsdd = 1) ? 1.5 ? ns clock delayed (tscd = 1) ? ?1.5 ? ns setup time t setup normal operation ? t cycle ?1.5 ? ns data delayed (tsdd = 1) ? t cycle ?3.0 ? ns clock delayed (tscd = 1) ? t cycle ?ns access time t access ?1.5?ns ts_clk ts_data t cycle t hold t setup t access l c www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 10 preliminary rev. 0.81 figure 3. mpeg-ts (rising launch, falling capture) timing diagram table 9. mpeg-ts specifications (rising launch, falling capture) parameter symbol test condition min typ max unit clock cycle time t cycle serial mode 11.3 ? 28.6 ns parallel mode 77 ? 8000 ns clock low time t clow serial mode (tsscr = 11) 5.1 ? 6.9 ns serial mode (tsscr = 00) 12.0 ? 15.8 ns parallel mode 39 ? 4000 ns clock high time t chigh serial mode (tsscr = 01) 5.1 ? 6.9 ns serial mode (tsscr = 11) 12.0 ? 15.8 ns parallel mode 39 ? 4000 ns hold time t hold normal operation ? t cycle /2 ? ns data delayed (tsdd = 1) ? t cycle /2 + 1.5 ? ns clock delayed (tscd = 1) ? t cycle /2?1.5 ? ns setup time t setup normal operation ? t cycle /2?1.5 ? ns data delayed (tsdd = 1) ? t cycle /2?3.0 ? ns clock delayed (tscd = 1) ? t cycle /2 ? ns access time t access ?1.5?ns ts_clk ts_data t cycle t hold t setup t access l c l www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 11 figure 4. eb/no (qef operation) vs. inpu t power for SI2107/08/09/10 (typical) sr = 27.5 mbaud, cr = 7/8 figure 5. ber after viterbi vs. eb/no for SI2107/08/09/10 5 5.5 6 6.5 7 7.5 8 8.5 -100 -80 -60 -40 -20 0 input power (dbm) eb/no (qef ) 975mhz 1550mhz 2150mhz 1318mhz 0.00000001 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 246810 eb/no (db) ber 27.5mbaud 1/2 27.5mbaud 2/3 27.5mbaud 3/4 27.5mbaud 5/6 27.5mbaud 7/8 all tests performed with 1550 mhz, C40 dbm input www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 12 preliminary rev. 0.81 figure 6. phase noise performance for SI2107/08/09/10 (typical) figure 7. frequency offset vs. carrier lock/ac quisition time for various baudrates using quicklock (typical) 0 0.05 0.1 0.15 0.2 0.25 0.3 -10 -5 0 5 10 frequency offset of desired channel (mhz) lock time (s ) 1 mbaud 2mbaud 5mbaud 10mbaud 20mbaud 35mbaud 45mbaud test conditions pin = ?40 dbm cr = 7/8 f = 1560 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 13 2. typical application schematics pwm lnb2 isen lnb1 vsen ts_data[7:0] vcc3_3 vcc3_3 vcc1_8 vcc3_3 vcc3_3 vcc3_3 vcc3_3 vcc3_3 vcc3_3 vcc1_8 vcc3_3 ts_clk reset ts_val ts_err int xtout sda scl ts_sync lnb supply circuit (si2108/10 only) or external lnb controller address select see table 16 note: balun matching components are placeholders only. actual values, if necessary, to be determined with specific layout and balun. note: transient voltage suppression device. part number and type to be dictated by surge requirements for the design. note: trace length to be 1/4 wavelength at midband. it is recommended that provision be allowed for tuning of the capacitor placement. for highest performance, please submit layout for review by silicon laboratories before pcb fabrication. c2 c2 tc2 tc2 c14 c14 in 2 nc 5 gnd 1 out2 6 gnd 3 out1 4 x1 balun transformer x1 balun transformer c36 c36 c8 c8 vdd_synth 36 vdd_lo 37 gnd 38 rfip1 39 rfin1 40 gnd 41 rfin2 42 rfip2 43 gnd 44 vdd_lna 1 rext 2 addr 3 vdd_mix 4 vdd_bb 5 vdd_adc 6 tdet/vsen 7 drc/lnb2 10 nc/isen 9 tgen/lnb1 8 reset 11 dcs/pwm 12 vdd_dig18 13 ts_data0 14 ts_data1 15 ts_data2 16 ts_data3 17 vdd_dig33 18 ts_clk 19 vdd_dig33 20 ts_data4 21 ts_data5 22 ts_data6 23 ts_data7 24 scl 25 sda 26 vdd_pll33 31 ts_val 28 xtal1 35 xtal2 34 xtout 32 vdd_xtal 33 int/rlk/gpo 30 ts_sync 27 ts_err 29 u1 SI2107/8/9/10 u1 SI2107/8/9/10 c6 c6 tc3 tc3 tc1 tc1 1 3 y1 y1 1 2 j1 j1 c7 c7 d4 d4 c5 c5 c15 c15 c3 c3 c9 c9 c11 c11 r2 r2 tc5 tc5 c19 c19 c4 c4 c12 c12 c13 c13 c10 c10 tc4 tc4 c1 c1 c16 c16 figure 8. SI2107/08/09/10 schematic www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 14 preliminary rev. 0.81 lnb vlnb_in vlnb_in for highest performance, please submit layout for review by silicon laboratories before pcb fabrication. c31 c31 r13 r13 r14 r14 q6 q6 c33 c33 r15 r15 q1 q1 c32 c32 r9 r9 q4 q4 r17 r17 d3 d3 r5 r5 r7 r7 q3 q3 r20 r20 q5 q5 r8 r8 r6 r6 c34 c34 l2 l2 pwm 12 isen 9 lnb2 10 lnb1 8 vsen 7 si2110 lnb control si2110 lnb control d1 d1 r16 r16 r12 r12 r10 r10 r11 r11 c30 c30 q2 q2 figure 9. diseqc 1.x lnb supply circuit www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 15 lnb vlnb_in vlnb_in for highest performance, please submit layout for review by silicon laboratories before pcb fabrication. q1 q1 q2 q2 l3 l3 c30 c30 r14 r14 r9 r9 r13 r13 c31 c31 r11 r11 q3 q3 r12 r12 l2 l2 r16 r16 d1 d1 r18 r18 r20 r20 c17 c17 c33 c33 r15 r15 r8 r8 c32 22 nf c32 22 nf q5 q5 r7 r7 pwm 12 isen 9 lnb2 10 lnb1 8 vsen 7 si2110 lnb control si2110 lnb control q4 q4 r10 r10 d3 d3 r5 r5 c35 c35 r6 r6 q6 q6 c34 c34 r17 r17 figure 10. diseqc 2.x lnb supply circuit www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 16 preliminary rev. 0.81 3. bill of materials table 10. SI2107/08/09/10 bill of materials component description vendor c1,c2,c4,c6,c10,c8,c9,c13,c14, c15,c16 0.1 f, x7r, 20% c5 0.01 f, x7r, 20% c3,c7,c11,c12 33 pf, 6 v, np0, 10% c19,c36 33 pf, 50 v, np0, 10% d4 transient voltage suppressor, 20 v 1 littlefuse smcj20ca j1 connector, f-type, 75 ? , 950-2150 mhz r2 4.53 k ? , 62.5 mw, 1% x1 balun transformer anaren b0922j7575a00 tc1-5 2 tuning components y1 20 mhz, 20 pf, 50 ppm, 20 ? esr u1 SI2107/08/09/10 silicon laboratories notes: 1. transient voltage suppression device should be selected to match the surge requirements of the application. 2. tuning component values depend on balun selected and layout . please contact silicon laboratories for assistance reviewing layouts and selecting matching components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 17 table 11. diseqc 1.x lnb supply bill of materials (si2108/10 only) component description vendor c30 47 f, 25 v, electrolytic, 20% c31 0.47 f, 25 v, x7r, 20% c32 22 nf, 25 v, x7r, 20% c33 0.22 f, 25 v, x7r, 20% c34 4.7 f, 25 v, x7r, 20% d1 cmpsh1-4, 40 v, 1 a zhcs750ta, 40 v, 750 ma central semiconductor zetex d3 mmbd1705, dual diode, 20 v, 25 ma fairchild l2 dr78098, 33 h, 1.2 a, 20% sd0705-330k-r-sl datatronic act q1 zxmn3b14 fdn337n zetex fairchild q2 fmmt618 zetex q3,q5,q6 mmbt3904 infineon q4 fmmt718 zetex r5 1.3 ? , 500 mw, 5% r6 33 ? , 250 mw, 5% r7 10 k ? , 62.5 mw, 5% r8 1 k ? , 250 mw, 5% r9 680 ? , 125 mw, 5% r10 0.22 ? , 1 w, 5% r11 22 k ? , 62.5 mw, 1% r12,r20 20 k ? , 62.5 mw, 5% r13 33 ? , 62.5 mw, 5% r14 43 k ? , 62.5 mw, 5% r15 3 k ? , 100 mw, 5% r16 2 k ? , 250 mw, 5% r17 2.2 k ? , 62.5 mw, 1% www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 18 preliminary rev. 0.81 table 12. diseqc 2.x lnb supply bill of materials (si2108/10 only) component description vendor c17 1200 pf, 25 v, x7r, 20% c30 47 f, 25 v, electrolytic, 20% c31,c35 0.47 f, 25 v, x7r, 20% c32 22 nf, 25 v, x7r, 20% c33 0.22 f, 25 v, x7r, 20% c34 4.7 f, 25 v, x7r, 20% d1 cmpsh1-4, 40 v, 1 a zhcs750ta, 40 v, 750 ma central semiconductor zetex d3 mmbd1705, dual diode, 20 v, 25 ma fairchild l2 dr78098, 33 h, 1.2 a, 20% sd0705-330k-r-sl datatronic act l3 dr78097, 100 h, 500 ma, 20% sd0504-101k-r-sl datatronic act q1 zxmn3b14 fdn337n zetex fairchild q2 fmmt618 zetex q3,q5,q6 mmbt3904 fairchild q4 fmmt718 zetex r5 1.3 ? , 500 mw, 5% r6 33 ? , 250 mw, 5% r7 10 k ? , 62.5 mw, 5% r8 1 k ? , 250 mw, 5% r9 680 ? , 125 mw, 5% r10 0.22 ? , 1w, 5% r11 22 k ? , 62.5 mw, 1% r12,r20 20 k ? , 62.5 mw, 5% r13 33 ? , 62.5 mw, 5% r14 43 k ? , 62.5mw, 5% r15 3 k ? , 100 mw, 5% r16 2 k ? , 250 mw, 5% r17 2.2 k ? , 62.5 mw, 1% r18 16 ? , 250 mw, 5% www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 19 4. part versions there are four pin- and software-compatible versions of this device. all versions include the l-band tuner, dvb- s/dss demodulator and channel decoder, and lnb signaling controller. furthermore, the si2108 and si2110 integrate an efficient lnb supply regulator while allowing operation with an external lnb supply regulator circuit. the lnb supply controller utilizes a step-up converter architecture. in case operation with an external regulator is de sired, SI2107 and si2109 can be used; these do not integrate the lnb step-up dc-dc controller. on the other hand, the si2109 and si2110 integrate an on-chip ?blindscan? accelerator, quickscan , which allows the implementation of a very fast channel scan, an important feature for end products targeted to free- to-air (fta) applications in which channel locations are unknown. SI2107 and si2108 do not integrate this accelerator and are a good fit when symbol rates and frequencies of satellite chann els are known, as in the case of pay-tv receivers or for fta receivers in which the embedded firmware cont ains the channel tuning information. table 13 summarizes the differences between part versions. table 13. device versions part number dvb-s/dss integrated tuner/ demodulator with integrated lnb messaging lnb supply regulator quickscan si2110 y y y si2109 y n y si2108 y y n SI2107 y n n www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 20 5. functional description the SI2107/08/09/10 is a fa mily of highly-integrated cmos rf satellite receiv ers for dvb-s and dss applications. th e device is an ideal solution for satellite set-top boxes, digital video recorders, digital televisions, and satellite pc-tv. the ic incorporates a tuner, demodulator, and lnb controller into a single device resulting in a significant reduction in board space and external component count. the device supports symbol rates of 1 to 45 mbaud over a 950 to 2150 mhz range. a full suite of features including automatic acquisition, fade recovery, blind scanning, performance monitoring, and diseqc? level 2.2 compliant signaling are supported. the si2110 an d si2108 further add short- circuit protection, overcurrent protection, and a step-up dc-dc controller to implement a low-cost lnb supply. furthermore, the si2109 and si2110 have an on-chip blindscan accele rator. an i 2 c bus interface is used to configure and monitor all internal parameters. 5.1. tuner the tuner is designed to accept rf signals within a 950 to 2150 mhz frequency range. the inputs are matched to a 75 ? coaxial cable in a single-ended configuration. the tuner block consists of a low-noise amplifier (lna), variable gain atte nuators, a local os cillator, quadrature downconverters, and anti-aliasing filters. the lna and variable gain stages provide balance between the noise figure and linearity characte ristics of the system. when all gain stages are combined, the device provides more than 80 db of gain range. the desired tuning frequency can be adjusted in intervals of 12.2 khz, without the aid of external varactors, using a unique two-stage tuning algorithm that is supplied wit h the software driver. the rapid settling time of t he local oscillator improves channel acquisition and switching performance. the pll loop filter has been comple tely integrated into the device resulting in low tuner phase noise, improved spurious response, and reduced bom cost. an external 20 mhz crystal unit generates the reference frequency for the system. 5.2. demodulator the demodulator su pports qpsk and bpsk demodulation of channels between 1 to 45 mbaud. it incorporates the following functional blocks: analog-to- digital converters (adcs), dc notch filters, i/q imbalance corrector, decimation filters, matched filters, equalizer, digital automatic gain controls, and a soft-decision decoder. the demodulator supports rapid channel acquisition using an advanced carrier offset estimation algorithm. when combined with the si2109/10?s blind scanning capabilities, the device becomes an ideal solution for the free-to-air (fta) and common interface (ci) market. automatic acquisition and fade recovery sequencers are also included to reduce the required amount of software interaction and to simplify the overall design. the output of the demodulator is quantized into a 4-bit number by the soft-decision decoder. the use of soft-decision decoding improves the error correction capabilit ies of the channel decoder. 5.3. dvb-s/dss channel decoder the SI2107/08/09/10 integrates a full-channel decoder, which can be configured in either dss or dvb-s mode and consists of a soft-decision viterbi decoder, de- interleaver, reed-solomon decoder, and energy- dispersal descrambler. 5.3.1. viterbi decoder the viterbi decoder performs maximum likelihood estimation of convolutional codes in compliance with dvb-s and dss standards. the decoder is capable of detecting code rate, puncturing pattern phase, 90 phase rotation, and i/q in terchange. supported code rates are listed in table 14 the device allows monitoring of the viterbi bit-error rate (ber) over a finite or in finite measurement window. 5.3.2. convolutional de-interleaver the deinterleaver disassembles the reed-solomon (rs) code words, which were interleaved by the modulator, to prov ide better resilience against burst errors. the SI2107/08/09/10 performs deinterleaving according to dvb-s and dss standards. 5.3.3. reed-solomon decoder the SI2107/08/09/10 supports rs codes in compliance with dvb-s and dss specifications. both standards use a shortened reed-solomon code, which can correct up to eight byte errors per information packet. dvb-s utilizes 204 byte codes. d ss utilizes 146 byte codes. table 14. viterbi code rates dvb-s dss 1/2 1/2 2/3 2/3 3/4 ? 5/6 ? ?6/7 7/8 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 21 the device allows monitoring of correctable bit, correctable byte, and uncorrectable packet errors over a finite or infinite measurement window. the device also includes a total ber monitor, which compares received data from a modulated prbs sequence against the same sequence generated from an on-chip prbs generator. 5.3.4. energy-dispersal descrambler the descrambler removes the energy dispersal scrambling introduced by the dvb-s process. the descrambler is automatica lly bypassed in dss mode. 5.4. on-chip bli ndscan controller: quick- scan (si2109/10 only) the device includes on-chip quickscan circuitry to facilitate extremely fast dete ction of available satellite channels. for each valid dvb-s/dss channel, the tuning frequency and symbol rate, which can be stored by the host for subsequent tuning, are determined. on SI2107/08 devices, the host needs to provide the channel tuning frequency and symbol rate to the device. 5.5. lnb signaling controller the device supports several lnb signaling methods including dc voltage select ion, continuous tone, tone burst, diseqc 1.x- and diseqc 2.x-compliant messaging, and several combinations of these to allow simultaneous operation with legacy tone/burst and diseqc-capable peripherals. SI2107/09 includes the capability to convert i 2 c signaling commands to signals that interface to an external lnb supply regulator circuit. in the case of (bi- directional) diseqc operation, the device modulates (and demodulates) the pwk data to (and from) an internal message fifo, which the host uses to write (and read) diseqc messages. in the case of transmission, the device can generate either the 22 khz tone burst directly or generate a tone envelope for when an external lnb supply controller is used, which includes the 22 khz oscillator. 5.6. on-chip lnb dc-dc step-up controller (si2108/10 only) next to the lnb message signaling controller, the device also integrates the lnb supply regulator controller. the supported lnb supply regulator architecture consists of a step-up dc-dc (boost) converter followed by an efficient filter, linefeed, and diseqc transmit/receive circuit, which implements a very power-efficient lnb supp ly solution. this facilitates a complete lnb supply circuit with only a minimal number of external components. 5.7. crystal oscillator the crystal oscillator requires a crystal with a resonant fundamental frequency of 20 mhz to generate the reference frequency for the local oscillator. a single crystal can be shared betw een two devices by utilizing the master-slave configuration shown in figure 11. figure 11. master-slave crystal sharing si21xx master si21xx slave xtout xtal2 xtal1 y1 c11 c12 xtal1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 22 6. operational description the following sections discuss the user-programmable functionality offered by the corresponding register map sections. refer to table 19, ?register summary,? on page 35 and detailed register descriptions starting on page 39. 6.1. system configuration the mpeg transport stream (ts) output interface carries the decoded satellite da ta to external devices for further processing. both dvb-s and dss receiver modes and associated output data packet formats are supported. mode selection is controlled via the system mode register, sysm. qpsk or bpsk demodulation is set via the modulation type (mod) register. the mpeg-ts output interface consists of the following output pins: ts_data[7:0] data ts_clk clock ts_sync sync/frame start indicator ts_val valid data indicator ts_err uncorrectable packet error the start of a ts frame is indicated by the ts_sync signal. the ts_sync signal is a pulse that is active during the sync byte in a dvb-s frame or during the first byte of a dss frame and is active only while ts synchronization exists. in serial mode, the ts_sync pulse can be programmed to be active for the whole byte, or the first bit only, by setting the tssl bit. the polarity of the ts_sync pulse can be programmed to be either active high or ac tive low using the tssp bit. the ts_val output is used to indicate when valid data is present. ts_val is active during the mpeg-ts frame packet data and inactive while parity data is being output or when there is no ts synchronization. the polarity of the ts_val output can be programmed to be active high or active low using the tsvp bit. the ts_err output indicate s that an uncorrectable error has been detected in the rs decoding stage and that the current ts data packet contains uncorrectable errors. the ts_err output is active during the entire erred ts frame. the polarity of ts_err can be programmed to be active high or active low using the tsep bit. all signals on the mpeg-ts output interface can be individually tri-stated us ing bits tse_oe, tsv_oe, tss_oe, tsc_oe, and tsd_oe. transport stream data can be output in a parallel byte- wide mode or a serial bit-wide mode for system-level flexibility. selection of the interface mode is controlled via the tsm bit. in serial mode, data is output on ts_data[0] while ts_data[7:1] are held low. the direction of the serial data stream may be programmed to output in an msb or lsb first direction using the tsdf bit. parity data may be optionally zeroed by setting the tspg bit. to support board-level timing modifications, the data stream may be delayed by setting tsdd. the transport stream clock can be programmed such that data is transitioning on its rising or falling edge using the tsce bit. in both serial and parallel mode, the transport stream clock mode bit, tscm, can be used to select either a gapped or continuous clock mode. in the gapped mode, the clock is active only when data is being output. for this, pa rity information is not considered data when the tspg is set to output zero data during parity. in the continuous mode, the clock runs without regard to data being output, and the user will use ts_val as a data strobe. to support board- level timing modifications, the clock stream may be delayed by register bit tscd. in serial mode, the transport stream clock rate range is determined by the tsscr register. the exact rate is determined during the acquisition process. the range that minimizes the difference between the effective transport stream data rate and the clock rate should be chosen. the recommended settings are listed in table 15. figure 12 illustrates paralle l data modes. figure 13 illustrates serial data modes. table 15. serial mpeg-ts clock frequency tsscr baud rate se rial clock rate 00 40?50 mbaud 80?88.5 mhz 01 30?40 mbaud 76.8?82.8 mhz 10 19?30 mbaud 54.9?59.2 mhz 11 1?19 mbaud 35?37.7 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 23 figure 12. mpeg-ts parallel mode figure 13. mpeg-ts serial modes the device has one output pin (pin 30), which can be configured as either a receiver lock indicator, general purpose output, or interrupt output, using the pin select register, psel. the receiver lock indicator provides a signal output for register bit rcvl. the general purpose output reflects the polarity of register bit gpo. the interrupt output is discussed further in ?6.2. interrupts?. the user can configure the device such that components of the channel decoder are bypassed. this is controlled by the energy-dispersal descrambler bypass bit, ds_bp, the reed-solomon decoder bypass bit, rs_bp, and the convolutional de-interleaver bypass bit, di_bp. the use of these bypass options is defined for the implementation of a ber test on a known modulated prbs data sequence as explained later in "6.5. channel decoder" on page 27. 6.2. interrupts the device is equipped with several sticky interrupt bits to provide precise event tracking and monitoring. next to interrupts being signaled via the i 2 c register map, the user can program one of the device terminals ts_data[7:0] ts_sync active high ts_val active high ts_err active high ts1 (sync) ts2 continuous parallel data mode ts_clk, rising edge ts188 ts1 (sync) ts2 rs1 data, parity start, active high valid, active high fail, active high ts1 (sync) ts2 gapped parallel data mode clk, falling edge+ gapped ts188 ts1 (sync) ts2 rs1 ts_clk rising edge continuous serial data mode ts_data[0] ts_val active low ts_err, active low ts188 rs1 ts1 (sync) ts2 ts_clk falling edge/ gapped ts_data[0] ts_sync active high ts2 ts2 ts1 (sync) ts1 (sync) ts188 rs1 gapped serial data mode ts2 ts1 (sync) ts_sync, active low/1-bit wide ts_val active high ts_err active high www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 24 (int) as a dedicated interrupt pin via the pin select register bit, psel. the devi ce contains an extensive collection of interrupt sources that can be individually masked from the int pin using the corresponding interrupt enable register bits, labeled with suffix ?_e?. thus, the int output is a logical-or of all enabled interrupts. generation of the channel interrupt on pin int can be masked off by us ing the interrupt enable bit, int_en. note that interrupt reporting in the register map is not affected by int_en. the interrupt signal polarity can be configured to be active high or active low using the interrupt polarity bit, intp. the interrupt signal type can be configured to be cmos output or open-drain/source output using the interrupt type bit, intt. interrupt bits are set by the device to 1 when an interrupt occurs. the host clears an interrupt bit by writing a 1 again, at which time the device resets the interrupt bit to zero. tabl e 16 illustrates the interrupt sources and their associated status, enable, and interrupt bits. table 16. events, interrupts, and status bits event interrupt bit e nable bit status bit receiver lock rcvl_i rcvl_e rcvl (0 ?>1) receiver unlock rcvu_i rcvu_e rcvl (1 ?> 0) agc lock agcl_i agcl_e agcl (0 ?> 1) agc failure agcf (0->1) agc threshold agcts_i a gcts_e agcts (0 ?> 1) carrier estimation lock cel_i cel_e cel (0 ?> 1) carrier estimation failure cef(0->1) symbol rate est. lock srl (0 ?> 1) symbol rate est. failure srf (0->1) symbol timing lock stl_i stl_e stl (0 ?> 1) symbol timing unlock stu_i stu_e stl (1 ?> 0) carrier recovery lock crl_i crl_e crl (0 ?> 1) carrier recovery unlock cru_i cru_e crl (1 ?> 0) viterbi lock vtl_i vtl_e vtl (0 ?> 1) viterbi unlock vtu_i vtu_e vtl (1 ?> 0) frame synchronizer lock fsl_i fsl_e fsl (0 ?> 1) frame synchronizer unlock fsu_i fsu_e fsl (1 ?> 0) acquisition fail aqf_i aqf_e aqf (0 ?> 1) c/n measurement complete cn_i cn_e viterbi ber measuremen t complete vter_i vter_e rs measurement complete rser_i rser_e message fifo empty fe_i fe_e message fifo full ff_i ff_e message received msgr_i msgr_e message parity error msgpe_i msgpe_e message receive timeout msgto_i msgto_e short-circuit detect scd_i scd_e over current detect ocd_i ocd_e blindscan done bsd o_i bsdo_e bsdo blindscan data read y bsda_i bsda_e bsda www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 25 6.3. receiver status during receive operation, the host can retrieve information on the status of agc lock (agcl), carrier estimation lock (cel), symbol rate estimation lock (srl), symbol timing lock (stl), carrier recovery lock (crl), viterbi decoder lock (vtl), frame sync lock (fsl), and overall receiver lock (rcvl). during channel acquisition, the host can retrieve information on error conditions due to: agc search (agcf), carrier estimation (cef), symbol rate search (srf), symbol timing search (stf), carrier recovery search (crf), viterbi code rate search (vtf), frame sync search (fsf), and overall receiver acquisition (aqf), 6.4. tuning control the SI2107/08/ 09/10 utilizes a unique two-stage tuning algorithm to provide optimal rf reception. the input signal is first mixed down to a low-if frequency by a coarse tuning stage and then down to baseband by a fine-tune mixer. the user programs both coarse and fine-tuning frequencies using the ctf and ftf registers. an algorithm (supplied with the reference software driver) is used to automatically calculate the required values. as part of the tuning process, the sample rate, fs, should also be programmed via the adcsr register. values between 192 and 207 mhz are supported. an algorithm is supplied with th e reference software driver to automatically select the optimal sampling rate. 6.4.1. automatic acquisition the receiver acquisition sequence consists of the following stages: analog agc search, carrier offset estimation, symbol rate estimation, symbol timing recovery, carrier recovery, viterbi search, and frame synchronization. for the receiver to lock, each stage must run to completion or declare lock as shown in figure 14. if a given stage is unable to achieve lock after exhausting a parameter search range or exceeding the timeout period, it asserts a fail signal. to initiate the acquisition sequence, the user should program the acquisition start bit, aqs. all search parameters must be specifie d before initiating the acquisition. upon completion of the acquisition sequence, the aqs bit is automatically cleared. the acquisition sequence can be aborted at any time by clearing the aqs bit. the status of the acquisition sequence can be monitored via the registers in the receiver status register map section. a successful acqu isition is reported by the assertion of the receiver lock bit, rcvl. a failed acquisition is reported by th e assertion of the acquisition fail bit, aqf. figure 14. acquisition sequence (symbol rate estimation available on si2109/10 only) 6.4.2. carrier offset estimation the desired carrier frequency may be offset from its nominal position due to the imperfections and temperature dependencies of the lnb. the carrier offset estimator uses a sear ch procedure to identify, track, and remove this frequ ency offset from the system. carrier offset estimation supports two modes: legacy mode and quicklock . quicklock features decreased search times and enhanced search ranges. silicon laboratories highly recommends the use of quicklock mode. legacy mode is supported for backwards compatibility with revi sion c of SI2107/08. the mode selection is programmed with the coems bit. acquisition start calibration lo tuning stage fail done lock lock lock done done analog agc search cfo estimation 1 symbol rate estimation 1 symbol timing loop 1 carrier frequency loop 1 viterbi search 2 frame search 2 receiver locked stage fail stage fail and stl unlocked stage fail stage fail stage fail stage fail but stl is locked 1. acquisition fail if stage fails n times in a row. 2. acquisition fail if stage completes parameter range without locking. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 26 in legacy mode, seven different carrier offset estimation search range scans can be programmed from 0.10 to ~6.0 mhz with register c esr. this mode locates frequency offsets when the carrier falls within the offset search range. smaller search ranges result in faster search times. in quicklock mode, an eighth carrier offset estimation search range is added. ranges from 0.10 to ~12.0 mhz can be programmed with register cesr. quicklock mode locates frequency offsets when the 3db bandwidth of the channel fa lls within the offset search range. when the search range is less than the channel bandwidth, quicklock search times further decrease. when using quicklock , set the inband power threshold, 2 db bandwidth threshold, and 3 db bandwidth threshold registers to the quicklock recommended default values before initiating an acquisition. refer to silic on laboratories application note ?an298: SI2107/08/09/10 application programming interface example software" for the recommended default values. the recommended values are documented in the signal acquisition section of the application note. when carrier offset estimati on is complete, the cel bit is asserted. if an error is detected during carrier offset estimation, the cef bit is set. carrier offset estimation commences under the control of the acquisition sequencer. after the completion of a search, the estimated carrier offset is stored in the carrier frequency error register, cfer. if no signal is found, the cef bit is asserted. the value contained in cfer may be optionally transferred to the cfo register to adjust the search center frequency and permit the utiliz ation of a smaller search range for subsequent acquisitions. this relationship can be expressed by the following equation: 6.4.3. carrier recovery loop the carrier recovery loop is responsible for acquiring frequency and phase lock to the incoming signal. when lock is achieved, the carrier recovery lock indicator, crl, is asserted. if carrier recovery lock is not achieved within a predefined timeout pe riod, the device declares carrier recovery failure by asserting the crf bit. the carrier recovery loop commences under the control of the acquisition sequencer. 6.4.4. symbol timing loop the symbol timing recovery loop is responsible for acquiring and tracking the symbol timing of the incoming data signal. when lock is achieved, the symbol timing loop lock indicator, stl, is asserted. if symbol timing lock is not achieved within a predefined timeout period, the device declares symbol timing loop failure by asserting the stf bit. the symbol timing recovery loop commences under the control of the acquisition sequencer. 6.4.5. automatic fade recovery the device is designed to au tomatically recover lock in the event of a fade condit ion. fade recovery is performed when any stage loses synchronization after receiver lock has been achieved. it is assumed that symbol rate, code rate, and puncturing pattern have not changed; so, these parameters remain fixed during the attempted reacquisition. the fade recovery sequence is shown in figure 15. the fade recovery sequence continues until either receiver lock is achieved or a new acquisition is initiated. figure 15. fade recovery sequence search center frequency f desired cfo + f s 2 15 -------- hz = unlock lock done analog agc search cfo estimation symbol timing loop carrier frequency loop viterbi search (limited) frame search receiver locked fail calibration lo tuning lock lock lock unlock unlock unlock unlock done www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 27 6.4.6. c/n estimator a carrier-to-noise estimator is provided to aid in satellite antenna positioning. the c/n measurement mode bit, cnm, controls whether the count is performed over a fixed-length or infinite window. with a fixed-length window, the window size is defined by register cnw. measurements are stored in a 16-bit saturating register, cnl. setting the c/n estimator start bit, cns clears the cnl register and initiates the c/n measurement. when operating in the finite window mode, the cns bit is automatically cleared when the measurement is complete. the cns bit must be cleared manually in the infinite mode to stop the count. an external lookup table is used to translate the measurement into a c/n estimate for a given setting of the c/n threshold, cnet, and a given digital agc setting. 6.5. channel decoder 6.5.1. viterbi decoder the viterbi decoder performs maximum likelihood estimation of convolutional codes in compliance with dvb-s and dss standards. when lock is achieved, the viterbi lock indicator, vtl, is asserted. if viterbi lock is not achieved after exhausting the specified parameter space, the device declares viterbi search failure by asserting the vtf bit. the viterbi search commences under the control of the acquisition sequencer. the device can be programmed to attempt to automatically acquire viterb i lock using all, one, or a subset of the supported code rates using the vtcs register. if lock is achieved, the status of the search, including code rate, puncturing pattern phase, 90-degree phase rotation, and i/q swap, can be monitored in the viterbi search status registers, vtrs, vtps, and vtiqs. 6.5.2. viterbi ber estimator the viterbi ber estimator measures the frequency of bit errors at the input of the viterbi decoder. the viterbi ber mode bit, vterm, controls whether the count is to be performed over a fixed length or infinite window. the window size is defined by vterw. the ber count is stored in a 16-bit saturating register, vt erc. setting the viterbi ber measurement start bit, vters, will clear the vterc register and initiate the measurement. when operating in the finite window mode, the vters bit will automatically be cl eared when th e measurement is complete. the vters bit must be cleared manually in the infinite mode to stop the count. 6.5.3. reed-solomon error monitor the reed-solomon error monitor is capable of counting bit, byte, and uncorrectable packet errors. the error type to be counted is controlled by the reed-solomon error type register, rsert. the reed-solomon error mode bit, rserm, controls whether the count is to be performed over a fixed length or infinite window. the window size is defined by rserw. the ber count is stored in a 16-bit saturating register, rserc. setting the rs ber measurement start bit, rsers, clears the rserc register and initiates the measurement. when operating in the finite window mode, the rsers bit is automatically cleared when the measurement is complete. the rsers bit must be cleared manually in the infinite mode, to stop the count. 6.5.4. prbs ber tester to facilitate in-system ps eudo random bit sequence (prbs) ber testing, the device provides the ability to synchronize and track test sequences contained in the payload (i.e. not sync bytes) of the mpeg data stream. the user can define the payload of each ts packet to exclude a number of header bytes, as set by prbs_header_size, a prbs test patter n must be encoded, modulated, and injected into the channel to be monitored. the device supports a prbs 223 - 1 bits long described by the following polynomial: to enable prbs testing, the reed-solomon error type register, rsert, must be appropriately programmed. after the device has synchronized to the incoming prbs test pattern, as indicated by prbs_sync, errors will be reported in th e rserc register. measurements can be performed at the output of the viterbi or reed-solomon decoder. to record errors at the output of the viterbi decoder, the reed-solomon decoder and interleaver must be bypassed by setting rs_bp and di_bp in the ?system configuration? section of the register map. to record errors at the output of the reed-solomon block, the rs_bp bit must be cleared. 6.5.5. frame synchronizer the output of the viterbi decoder is aligned into bytes by detecting sync patterns within the data stream. in dvb- s systems, the sync byte, 47 h, occurs during the first byte of a 204 byte rs code block. in dss systems, a sync byte, 1dh, is appended to the beginning of each rs encoded 146-byte block, resulting in 147-byte rs code blocks. in dss mode, sync bytes are discarded before the byte stream is output to subsequent decoding stages. when lock is achieved, the frame gx () x 23 x 18 1 ++ = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 28 synchronization lock bit, fsl, is asserted. if lock is not achieved, the frame synchronizer fail bit, fsf, is asserted. the frame synchronizer commences under the control of the acquisition sequencer. following frame synchronization lock, the device examines the byte stream for a possible 180-degree phase shift. if an inversion is detected, data are inverted prior to being output. 6.6. automatic gain control the SI2107/08/09/10 is equ ipped with the ability to adjust signal levels via an automatic gain control (agc) loop. this ensures that the noise and linearity characteristics of the signal path are optimized at all times. agc settings can be set at 4 points in the analog signal chain and 2 points in the digital signal chain. 6.6.1. analog agc system gain is distributed into four independent stages as shown in figure 16. the gain range of all stages combined is over 80 db. when the agc search completes, the agcl bit is asserted. if an error is encountered during the agc search, the agcf bit is also set. the agc search commences under the control of the acquisition sequencer. the agc loop works to automa tically adjust the gain of each stage to minimize the error between a measured signal power and a desired output level. signal power is measured at the output of the adc using an internal rms power calculator. the resu lt is stored in a 7-bit saturating register, agcpwr. the desired output level is stored in the agc threshold register, agcth. signal power measurements occur at a frequency dictated by the agc measurement window size, agcw. this frequency can be described using the following equation, where fs equals the adc sampling rate, adcsr. when gain adjustments are made, the device allows up to 100 s for the gain changes to settle before beginning the next measurement. to facilitate a rapid initial acquisition, SI2107/08/09/10 includes an acquisition mo de wherein the measurement window size is reduced by a factor of 64 when compared to the normal tracking mode. during the agc search, the de vice is in acquisition mode, and the gain is adjusted until the measured signal power crosses the desired threshold or a limit is reached. if the signal po wer crosses the threshold before reaching a limit, the search completes, and the agcl bit is asserted. if a gain limit is reached, the device asserts both the agcl bit and the agcf bit. in the normal tracking mode, the device continuously measures the input signal power according to the agc measurement window size. if the absolute value of the difference between the agcth and agcpwr exceeds the value of the agc tracki ng threshold, agctr, the agc loop adjusts gain settin gs until the agcpwr level matches agcth. the agc gain offset register, agco, provides the ability to apply a static gain offset to the input channel. silicon laboratories will provide the recommended values for this register. it is possible to read out the instantaneous settings of each of the four vgas from the agc, , registers. figure 16. analog agc control loop agc measurement frequency f s agcw ------------------- hz = lna vga1 vga2 offset a/d agc rms calculator agc threshold lpf mixer www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 29 6.6.2. digital agc downstream of the analog vgas, after a/d conversion of the signal, there are two points at which the digital gain can be programmed. digital agc1 is used to change signal power after removal of adjacent channels by the (digital) anti-aliasing filter. by default, dagc1 is enabled and periodically adjusts the gain of the i & q data streams based on a comparison of the measured complex rms level and a target value. the target value can be selected with the dagc1t register. two levels are provided to allow operation with additional headroom for signal peaks during signal acquisition. th e gain function of dagc1 can be disabled using dagc1_en; then, no gain is applied to i & q data streams. the signal measurement and gain adjustment normally operate continuously, allowing the gain to trac k the input level. the measurement window can be adjusted by register dagc1w. the automatic updating of the gain can be frozen by register bit dagc1hold. this holds the gain to the last setting. the value of the gain can be read from the dagc1 register. it is possible to override the internal agc algorithm and provide host-based control of agc1 by appropriately programming register bit dagc1host. digital agc2 (dagc2) is inte nded to optimally scale the soft decision outputs of the demodulator prior to viterbi decoding. this allows it to compensate for signal level variations after matched filtering and equalization. normally, operation is continuous, but tracking can be disabled using register bit dagc2_tdis. this holds the gain to the last setting. during agc operation, the average power of the signal is compared to a threshold set by register dagc2t. the signal power is measured over a finite window specified by dagc2w. the gain applied to the signal to make the input match the programmed threshold can be read from register dagc2ga. 6.7. lnb signaling controller all device versions provide lnb signaling capability. the device supports several lnb signaling methods including dc voltage select ion, continuous tone, tone burst, diseqc 1.x- and diseqc 2.x-compliant messaging. a description of each method follows. 6.7.1. dc voltage selection a constant dc voltage of 18 or 13 v is typically used to switch the lnb between horizontal and vertical polarity or clockwise and counterclockwise polarization. the lnbv bit is used to select the desired voltage. when an external lnb supply regulator is used, the dcs pin is driven high or low depending on the selection of high or low voltage. 6.7.2. tone generation tone-related information is communicated to external devices via the tgen pin. th e tone format select bit, tfs, specifies whether the output of tgen is an internally-generated tone or a tone envelope. the frequency of the internal tone generator is governed by the following equation: frequencies between 20 and 24 khz are supported. the default value of tfq results in a nominal tone frequency of 22 khz. when tone envelope output is selected, a high signal on tgen corresponds to "tone on" while a low signal corresponds to "tone off." when operating in the ?manual lnb messaging mode?, the tt bit directly controls the ou tput of the tone or tone envelope. 6.7.2.1. continuous tone a continuous tone is typica lly used to select between the high and low band of an incoming satellite signal. the lnbct bit can be set to one to generate a continuous tone. 6.7.2.2. tone burst the tone burst signaling method can be used to facilitate the control of a simple two-way switch. two types of tone burst are available, as shown in figure 17. an unmodulated tone burst persists for 12.5 ms. a modulated tone burst lasts for the same duration but consists of a sequence of nine 0.5 ms pulses and 1 ms gaps. tone burst selection is controlled via the lnbb bit. the tone burst command can optionally be disabled to support systems that do not use tone burst signaling by setting the burst disable bit, brst_ds, to one. this disables the tone/burst generation as part of the diseqc signaling sequence when the device uses ?automatic lnb messaging mode? as described below. figure 17. tone burst modulation f tone 100 32 tfq 7:0 [] 1 + () [] ---------------------------------------------------------- mhz = '0' tone burst (satellite a) envelope envelope tone 12.5 ms '1' tone burst (satellite b) tone www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 30 6.7.3. diseqc? the diseqc signaling method extends the functionality of the legacy 22 khz tone by superimposing a command protocol and adding an optional return channel. a diseqc command normally consists of a framing byte, an address byte, a command byte, and, optionally, one or more data bytes. this format is illustrated in figure 18. figure 18. diseqc message format the length of a message is specified by msgl. when the message length is set to one byte, the message is modulated using tone burst modulation. when the message length is set to two or more bytes, the message is modulated using diseqc-compliant modulation, and the odd parity bit is automatically added. the diseqc modulation scheme is illustrated in figure 19. figure 19. diseqc compliant modulation 6.7.3.1. diseqc 1.x one-way communication messages are programmed directly into the device using a message fifo that consists of six byte wide registers, fifo1?6. the messages must be written in a first-in-first-out manner such that the first byte of a message is stored in fifo1; the second byte is stored in fifo2, and so on. if messages are longer than six bytes, the device asserts the fifo empty indicator, fe, as soon as the sixth byte has been read. the lnb control module then takes its next byte from fifo1 and continues the process. the message length must also be reprogrammed to indicate how many more bytes remain to be sent. the interval between fifo reads is typically 13.5 ms. to support cascaded diseqc devices, it may be necessary to repeat commands. repeated commands should be separated by at least 100 ms to ensure that the far-end device is connected to the signaling path. to facilitate the required 10 0 ms delay, a four byte command can be inserted between repeated commands. 6.7.3.2. diseqc 2.x two-way communication two-way communication is supported via diseqc 2.x- compliant messages. when the seventh bit in the framing byte of an outgoing message is set to 1, the device anticipates a response and monitors the line for up to 150 ms for an incoming message. if no message is detected during the 150 ms monitoring period, the msgto bit is asserted to indicate the time-out condition. a diseqc reply me ssage typically consists of a single framing byte and optionally one or more data bytes as shown in figure 20. figure 20. diseqc reply format when a complete message has been received (one or more bytes followed by 4 ms of silence), the msgr bit is asserted. should parity errors exist in the received message, the msgpe flag is also asserted. if the received message is longer than 6 bytes, the fifo full bit, ff, is asserted to indicate that a byte has been written to fifo6. the lnb control module writes the next byte to fifo1. the length of the received message is recorded in the msgrl register. 6.7.4. lnb signaling modes the lnb signaling modes are described in the following sections. 6.7.4.1. automatic lnb messaging mode the SI2107/08/09/10 lnb signaling controller can fully manage the generation and sequencing of all lnb commands. the device is configured in this mode by appropriately programming the lnb messaging mode register, lnbm. to initiate a message sequence, the user should first program lnb voltage selection (lnbv), continuous tone enable (lnbct), tone burst type (lnbb), and diseqc message parameters (mmsg, msgl, and fifo1..6). subsequently, the lnb sequence start bit, lnbs, must be set to start the automated transmission sequence. the device automatically allocates the required delays between each signaling method. prior dc voltage levels and continuous tones, if present, persist until the sequence is initiated. a typical sequ ence is shown in figure 21. multiple messages can be sent in a sequential manner by setting the mmsg bit. when this bit is set, the lnb control module delays continuous tone and tone burst commands until all messages in the sequence have been sent. after the current message is transmitted, the mmsg bit is automatically cleared. the tone burst can be disabled as part of this sequence depending on the setting of brst_ds. address command data pp pp framing '0' data bit '1' data bit 1.0 ms 0.5 ms 0.5 ms 1.0 ms data pp p data framing www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 31 when the sequence has comp leted, the device clears the lnb sequence start bi t, lnbs, automatically. note that, when operating in this mode, the drc pin is high while transmitting and low while receiving. 6.7.4.2. step-by-step lnb messaging mode by appropriately programming the lnb messaging mode register, lnbm, the device allows for individual control of each signaling method by the host. in this mode, the lnb voltage, lnbv, and lnb continuous tone enable, lnbct, take effect once they are set without waiting for the user to set the lnb sequence start bit, lnbs. the diseqc message uses the lnbs bit to start transmission and behaves the same as in automatic lnb messaging mode. however, the guard intervals between each signaling method (lnb voltage change, diseqc message, tone burs t, and continuous tone resumption) are controlled by the host. in this mode, the tone burst should be implemented by using a 1-byte diseqc message of all 0s or all 1s programmed into fifo1. the device uses appropriate modulation for the tone burst; i.e., when fifo1 is programmed to 00h (rather than a diseqc-compliant modulation for a '00h' byte), no tone is generated. also, the device does not expect a reply if fifo1 is programmed to ffh; i.e., the assertion of bit7 is not considered a request for the peripheral to reply in step- by-step lnb messaging mode. 6.7.4.3. manual lnb messaging mode the manual lnb messaging mode provides the maximum level of signaling flexibility but at the expense of increased software interaction. the device is configured in this mode by appropriately programming the lnbm register. the continuous tone, tone burst, and messaging controls are not functional in this mode. when the tone format bit, tfs, is programmed for use of the internal oscillator, assertion of the tt bit modulates the output of the internal tone generator on the tgen pin, and the tr bi t records the envelope of a tone presented to the tdet pin. when the tone format select bit, tfs, is programmed to use an external oscillator, th e tt bit directly controls the output of the tgen pin, and the tr bit directly reflects the input of the tdet pin. in this mode, the tone direction control bit, tdir, directly controls the output of the drc pin. figure 21. lnb signaling sequence end of continuous tone (if present) start of continuous tone (if present) 1st message (no reply requested) 2nd message (reply requested) reply to 2nd message tone burst > 15ms > 25ms > 15ms > 15ms < 150ms change of voltage (if required) www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 32 6.8. on-chip ln b dc-dc step-up controller (si2108/10 only) in addition to the lnb signaling controller present on all device versions, si2108 and si2110 devices contain an internal supply controller circuit. this internal dc-dc controller can be enabled via register bit lnb_en. the internal circuit requires th e connection of an external circuit with a specified b ill-of-materials, and this combination generates the selected lnb voltage with superimposed one-way or two-way lnb signaling communications. si2108/10 devices include short- circuit protection, overcurrent protection, and a step-up dc-dc controller to implement a low-cost lnb power supply using minimal external components. the required circuit for diseqc1.x operation is illustrated in figure 9 on page 14. a circuit for diseqc2.x operation is shown in figure 6 on page 12. when the lnb supply circui t is populated, the si2108/ 10 detects a connection to ground on the isen pin via r10 during reset and configures the lnb pins for dc-dc converter control instead of providing the interfaces to an external lnb supply regulator discussed in the previous section. see table 17. the lnb supply controller is di sabled by default. to use the supply, it must be enabled by setting the lnb enable bit, lnb_en. if the lnb suppl y circuit is connected, the tfs bit is ignored; the internal lnb supply controller uses its internal oscillato r to generate the 22 khz tone. the tfq setting can still be us ed to modify the nominal frequency as explained earlier. selection of high or low voltage outputs the corresponding pwm control signal for the boost converter. to compensate for long cable lengths, a 1 v boost can be applied to both levels by setting the comp bit. the nominal level of both the low- and high-output voltages can be further fi ne-tuned using the vlow and vhigh registers. register bit lnbv selects whether to output high or low dc voltage to the lnb. during operation, the voltage level of the line can be monitored via the vmon register. the maximum current draw of the lnb supply can be set using the imax register. the overcurrent threshold of the lnb supply may be set via the ilim register. if the output current exceeds this value, the external lnb power supply is automatically disabled, and the overcurrent detect bit, ocd, is asserted. the device attempts to restore normal operation after 1 s by supplying power to the line. during the recovery period, overcurrent detection is disabled for the time specified by the olot register. short circuit protection circuitry operates in conjunction with overcurrent detection to ra pidly identify short-circuit conditions. if the output is shorted to ground, the external lnb power supply is automatically disabled, and the short-circuit detect bit, scd, is asserted. the device attempts to restore normal operation after one second by supplying power to the line. during the recovery period, short-circuit detection is disabled for the time specified by the slot register. the lnb supply circuit is protected from an overvoltage condition by design. in the event that the lnb supply circuit is accidentally connected to a voltage source greater than the intended output voltage, it remains operational. the lnb supply circuit resumes normal operation when the connection to the external voltage source has been removed. 6.9. on-chip blindscan controller: quickscan (si2109/10 only) quickscan is comprised of a two stage process: a blindscan stage and confirmation stage. it is an automated process whereby the minimum and maximum rf frequency and symbol rate limits are entered in the following registers bs_fmin, bs_fmax, srmin, and srmax. after b lindscan is completed, the host may further use the resulting candidate channel information (channel center frequencies and baud rates) to try to actually acquire such channels by locking the receiver to them. further information such as c/n, ber, channel program ids, and etc. can be obtained once the receiver locks to a candidate channel. through this confirmation proce ss, any falsely identified channels can be rejected. 6.9.1. programming sequence if quickscan is conducted whereby the symbol rate search range is above 12.5 mbaud (for example srmin = 2 mbaud and srmax = 20 mbaud) silicon laboratories recommends that blindscan is performed twice to ensure the most favorable estimates of channel frequencies and symbol rates. the programming sequence is as follows: 1. program the frequency range (bs_fmin, bs_fmax) and symbol rate range (srmin, srmax) values over which to perform blindscan. table 17. lnb pin configuration pin lnb supply circuit connected unconnected 7 vsen tdet 10 lnb2 drc 9 isen nc 8lnb1tgen 12 pwm dcs www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 33 a. default values i. srmin = 0 mbaud ii. srmax = 0 mbaud iii. bs_fmin = 825 mhz iv. bs_max= 2087 mhz the default values for the minimum and maximum symbol rates are zero. enter minimum and maximum symbol rates. recommended values are srmin = 1 mbaud and srmax = 45 mbaud for discovery of all possible dvb- s channels. 2. program the following registers with the following parameters. a. lsa control register 1. the length of the time averaging window is set by setting avg_win. the averaging removes uncorrelated noise from the spectrum. b. tilt correction threshold register. a correction can be applied to the spectrum to compensate for "tilts" in the spectrum due to frequency dependent attenuation such as poor cables for example. c. reference noise level margin threshold register. this sets the power level threshold for the detection of channels. d. 1 db bandwidth threshold register. this sets the tolerance level for determination of the 1 db bandwidth for a detected channel. e. 2 db bandwidth threshold register. this sets the tolerance level for determination of the 2 db bandwidth for a detected channel. f. 3 db bandwidth threshold register. this sets the tolerance level for determination of the 3 db bandwidth for a detected channel. g. inband power threshold register. this sets the threshold for determining the drop in power in a detected channel to determine the channel bandwidth. important: it is highly recommended that the registers in step 2 be programmed with default values provided by silicon laboratories. refer to ?an298: SI2107/08/09/ 10 application programming interface example software?, for the recommended values. the values are documented in the quickscan section of the application note. silicon laborat ories has tested quickscan under real world conditions in a number of countries and the recommended values provide the best performance. 3. clear the following host control register bits. a. sr_ctrl_host b. adcsr_ctrl_host c. ctf_ctrl_host d. ftf_ctrl_host important : these bits should be returned to their default settings (allowing host control) if the user wants to tune to individual channels following blindscan for single channel acquisition. 4. set bs_start in the blind scan control register. this initiates the blindscan process. 5. wait for either bsda (or in terrupt bsda_i) or bsdo (or interrupt bsdo_i) to be set. 6. take the following actions depending on which condition is present: a. when bsda (or bsda_i) is set: the device has found a potential dvb-s or dss (depending on the part's operating mode) channel. the host can read out: i. bs_ctf, bs_ftf, cfer, and bs_adcsr to determine the channel's rf frequency from the following formula: rf(mhz) = bs_ctf x 10 + {bs_ftf(decimal) + cfer (decimal)} x bs_adcsr note: the registers bs_ftf with a fixed format of <15,14> and cfer with a fixed format of <16,15> are 2's complement numbers which need to be converted into decimal numbers first. ii. srest to determine the channel's symbol rate estimate from the following formula: symbol rate (mbaud) = srest x bs_fs / 2^23 where bs_fs = bs_adcsr x 1 mhz iii. upon reading these registers, the host should clear the bsda & bsda_i bits. go back to step 6. b. when bsdo (or bsdo_i) is set: the blindscan operation is complete within the rf and symbol rate search ranges. the device automatically clears bs_start. 7. repeat steps 1 through 6 with the change in values for the following parameters if the sy mbol rate search range is below 12.5 mbaud. a. set srmin to 12.5 mbaud. b. keep srmax the same value from the first pass. c. set inband power threshold register to the second recommended default value. d. set 2 db bandwidth threshold register to the second recommended default value. 8. end of blindscan operation. the final set of estimates for rf center frequencies and associated symbol rates can be used by the host to lock to the detected channels to obtain channel information such as channel id for example. also at this point channels falsely identified during blindscan can be rejected upon failure to lock. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 34 7. i 2 c control interface the i 2 c bus interface is provi ded for configuration and monitoring of all internal registers. the SI2107/08/09/10 supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. individual data transfers to and from the device are 8-bits. the i 2 c bus consists of two wires: a serial clock line (scl) and a serial data line (sda). the device always operates as a bus slave. read and write operations are performed in accordance with the i 2 c-bus specification and the following sequences. the first byte after the start condition consists of the slave address (slave adr, 7-bits) of the target device. the slave address is configured during a hard reset by setting the voltage on the addr pin. possible slave addresses and their corresponding addr voltages are listed in table 18. four addresses are available, allowing up to four devices to share the same i 2 c bus. the r/w bit determines the direction of data transfer. during a read operation, data is sent from the device to the bus master. during a write, data is sent from the bus master to the device. the field labeled ?data (adr)? must contain the 8-bit address of the target register. the data to be transferred to or from the target register must be placed in the following 8-bit ?data? field. when the auto-increment feature is enabled, inc_ds, the target register address, is automatically incremented for subsequent data transfers until a stop condition ends the operation. some registers in the device are larger than the 8-bit data field permitted by i 2 c. these registers are split into 8-bit addressable chunks that are uniquely identified by a positional suffix. the suffix l indicates the low-byte; the suffix m indicates the middle-byte (for 24- bit registers only), and the suffix h indicates the high- byte. to read a multibyte register as a single unit, the low byte must be read first. this forc es the device to sample and hold the contents of the remaining bytes until the multibyte read is complete. if a stop condition occurs before the operation is complete, the buffered data is discarded. to write a multibyte register as a single unit, the low byte must be written first. all bytes must be transferred to the device before the multibyte value is recorded. if a stop condition occurs before the operation is complete, the buffered data is discarded. the slave address consists of a fixed part and a programmable part. the voltage of the addr pin is used to set the two least significant bits of the address during device power-up according to the table below. this enables up to four de vices to share the same i 2 c bus. figure 22. i 2 c interface protocol table 18. i 2 c slave address selection fixed address lsbs addr voltage (v) 11010 00 v 3.3 (pullup) 11010 01 2/3 x v 3.3 10% 11010 10 1/3 x v 3.3 10% 11010 11 0 (pulldown) read operation write operation s slave adr w a data (adr) a s r or p slave adr r a data a/a p s slave adr w a data (adr) a s r or p slave adr w a data a/a p n bytes + ack n bytes + ack a = acknowledge s = start condition r = read (1) p = stop condition w= write (0) s r = repeated start condition master slave www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 35 8. control registers the control registers can be divided into three main clas ses: initialization, run-time , and status. initialization registers (?i?) need only be programmed once following device power-up. run-time registers (?rt?) are the primary registers for device control. status registers (?s?) provid e device state information. the corresponding category of each register is indicated in the rightmost column of table 19. unused register bits of a register byte are reserved, their bit values should not be changed from the default values, as identified below under the description of each individual register byte. table 18 lists all registers available in si2110; some registers may not be available in other part versions, as identified below under the description of each individual register byte. table 19. register summary name i 2 c addr. d7 d6 d5 d4 d3 d2 d1 d0 system configuration device id 00h dev[3:0] rev[3:0] s system mode 01h inc_ds mod[1:0] sysm[2:0] i ts ctrl 1 02h tsep tsvp tssp tssl tscm tsce tsdf tsm i ts ctrl 2 03h tspcs tscd tsdd tspg tsscr[1:0] i pin ctrl 1 04h int_en intt intp t se_oe tsv_oe tss_oe tsc_oe tsd_oe i pin ctrl 2 05h gpo psel[1:0] i bypass 06h ds_bp rs_bp di_bp i interrupts int en 1 07h rcvl_e agcl_e cel_e stl_e crl_e vtl_e fsl_e i int en 2 08h rcvu_e agcts_e stu_e cru_e vtu_e fsu_e aqf_e i int en 3 09h cn_e vter_e rser_e m sgpe_e fe_e ff_e msgr_e msgto_e i int en 4 0ah bsdo_e bsda_e scd_e ocd_e i int stat 1 0bh rcvl_i agcl_i cel_i stl_i crl_i vtl_i fsl_i s int stat 2 0ch rcvu_i agcts_i stu_i cru_i vtu_i fsu_i aqf_i s int stat 3 0dh cn_i vter_i rser_i msgpe_i fe_i ff_i msgr_i msgto_i s int stat 4 0eh bsdo_i bsda_i scd_i ocd_i s receiver status lock stat 1 0fh agcl cel srl stl crl vtl fsl s lock stat 2 10h rcvl bsda bsdo s acq stat 11h aqf agcf cef srf stf crf vtf fsf s www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 36 preliminary rev. 0.81 tuning control acq ctrl 1 14h aqs rt adc sr 15h adcsr[7:0] rt coarse tune 16h ctf[7:0] rt fine tune l 17h ftf[7:0] rt fine tune h 18h ftf[14:8] rt ce ctrl 29h cesr[2:0] i ce offset l 36h cfo[7:0] rt ce offset h 37h cfo[15:8] rt ce err l 38h cfer[7:0] rt ce err h 39h cfer[15:8] rt sym rate l 3fh sr[7:0] rt sym rate m 40h sr[15:8] rt sym rate h 41h sr[23:16] rt cn ctrl 7ch cns cnm cnw[1:0] i cn th 7dh cnet[7:0] i cn l 7eh cnl[7:0] rt cn h 7fh cnl[15:8] rt channel decoder vt ctrl 1 a0h vtcs[5:0] i vt ctrl 2 a2h vters vterm vterw[1:0] rt vt stat a3h vtrs[2:0] vtps vtiqs s vt ber cnt l abh vterc[7:0] rt vt ber cnt h ach vterc[15:8] rt rs err ctrl b0h rsers rserm rserw rsert[1:0] rt rs err cnt l b1h rserc[7:0] rt rs err cnt h b2h rserc[15:8] rt ds ctrl b3h dst_ds dso_ds i prbs ctl b5h prbs_ start prbs_ invert prbs_ sync prbs_header_size rt table 19. register summary (continued) name i 2 c addr. d7 d6 d5 d4 d3 d2 d1 d0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 37 automatic gain control agc ctrl 1 23h agcw[1:0] i agc ctrl 2 24h agctr[3:0] agco[3:0] i agc 1?2 gain 25h agc2[3:0] agc1[3:0] i agc 3?4 gain 26h agc4[3:0] agc3[3:0] i agc th 27h agcth[6:0] i agc pl 28h agcpwr[6:0] s dagc 1 ctrl 75h dagc1_en dagc1w[ 1:0] dagc1t dagc1hold dagc1host i dagc1 l 76h dagc1[7:0] i dagc1 h 77h dagc1[15:8] i dagc2 ctrl 78h dagc2[3:0] dagc2w[1:0] dagc2tdis i dagc2 th 79h dagc2t[7:0] i dagc2lvl l 7ah dagc2ga[7:0] i dagc2lvl h 7bh dagc2ga[15:8] i lnb supply controller lnb ctrl 1 c0h lnbs lnbv lnbct lnbb mmsg msgl[2:0] rt lnb ctrl 2 c1h lnbm[1:0] brst_ds tfs rt lnb ctrl 3 c2h tdir tt tr rt lnb ctrl 4 c3h tfq[7:0] rt lnb stat c4h fe ff msgpe msgr msgto msgrl[2:0] s msg fifo 1 c5h fifo1[7:0] rt msg fifo 2 c6h fifo2[7:0] rt msg fifo 3 c7h fifo3[7:0] rt msg fifo 4 c8h fifo4[7:0] rt msg fifo 5 c9h fifo5[7:0] rt msg fifo 6 cah fifo6[7:0] rt lnb s ctrl1 cbh vlow[3:0] vhigh[3:0] i lnb s ctrl2 cch ilim[1:0] im ax[1:0] slot[1:0] olot[1:0] i lnb s ctrl3 cdh vmon[7:0] s lnb s ctrl4 ceh lnbl lnb_en comp lnbmd i lnb s stat cfh scd ocd s table 19. register summary (continued) name i 2 c addr. d7 d6 d5 d4 d3 d2 d1 d0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 38 preliminary rev. 0.81 quickscan host ctrl 1ch sr_ ctrl_ host adcsr_ ctrl_host ctf_ctrl_ host ftf_ctrl_ host i rs est l 31h srest[7:0] rt rs est m 32h srest[15:8] rt rs est h 33h srest[23:16] rt sr est ctrl 2 3ah false_ala rm_proc_ en i sr max 42h srmax[7:0] i sr min 43h srmin[7:0] i bs ctrl 80h bs_ start bsda coesm rt bs minfreq l 81h bs_fmin[7:0] i bs minfreq m 82h bs_fmin[15:8] i bs minfreq h 83h bs_fmin[17:16} i bs maxfreq l 84h bs_fmax[7:0] i bs maxfreq m 85h bs_fmax[15:8] i bs maxfreq h 86h bs_fmax[17:16} i bs coarsefreq 89h bs_ctf[7:0] rt bs finefreq l 8ah bs_ftf[7:0] rt bs finefreq h 8bh bs_ftf[14:8] rt bs pll div 8ch bs_adcsr[7:0] rt lsa ctrl 1 8dh avg win[6:5] i spectrum tilt correction threshold 8eh spec_tilt_correc[7:0] i 1db bw threshold 90h bw_1db[7:0] i 2db bw threshold 91h bw_2db[7:0] i 3db bw threshold 92h bw_3db[7:0] i inband power threshold 93h inband_threshold[7:0] i noise level margin threshold 94h ref_noise_margin[7:0] i table 19. register summary (continued) name i 2 c addr. d7 d6 d5 d4 d3 d2 d1 d0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 39 register 00h. device id register bit d7 d6 d5 d4 d3 d2 d1 d0 name dev[3:0] rev[3:0] bit name function 7:4 dev[3:0] device id. 0h = si2110 1h = si2109 2h = si2108 3h = SI2107 3:0 rev[3:0] revision. current revision = 4h register 01h. system mode bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 inc_ds mod[1:0] sysm[2:0] bit name function 7:6 reserved program as shown above. 5 inc_ds i 2 c automatic address increment disable. 0 = enabled (default) 1=disabled 4:3 mod[1:0] modulation selection. 00 = bpsk demodulation 01 = qpsk demodulation (default) 10 = reserved 11 = reserved 2:0 sysm[2:0] system mode. 000 = dvb-s (default) 001 = dss 010?111 = reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 40 preliminary rev. 0.81 register 02h. transport stream control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name tsep tsvp tssp tssl tscm tsce tsdf tsm bit name function 7 tsep transport stream error polarity. 0 = active high (default) 1 = active low 6 tsvp transport stream valid polarity. 0 = active high (default) 1 = active low 5 tssp transport stream sync polarity. 0 = active high (default) 1 = active low 4tssl transport stream start length. 0 = byte wide (default) 1 = bit wide note: this bit is ignored in parallel mode. 3tscm transport stream clock mode. 0 = gapped mode (default) 1 = continuous mode 2tsce transport stream clock edge. 0 = data transitions on rising edge (default) 1 = data transitions on falling edge 1tsdf transport stream serial data format. 0 = msb first (default) 1 = lsb first note: this bit is ignored in parallel mode 0tsm transport stream mode. 0 = serial (default) 1 = parallel www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 41 register 03h. transport stream control 2 bitd7d6d5d4d3d2d1d0 name 0 tspcs tscd tsdd tspg tsscr[1:0] bit name function 7:6 reserved program as shown above. 5 tspcs transport stream parallel clock smoother. smoothens ts_clk to ~50% duty cycle. 0 = smoothing disabled 1 = smoothen clock to ~50% duty cycle (default) 4tscd transport stream clock delay. adds delay to ts_clk to adjust clock-data timing relationship. 0 = normal operation (default) 1 = delay clock relative to data 3tsdd transport stream data delay. adds delay to ts_data, ts_sync, ts_val, ts_err output to adjust clock-data timing relationship. 0 = normal operation (default) 1 = delay data relative to clock 2 tspg transport stream parity gate. 0 = normal operation (default) 1 = zero data lines during parity 1:0 tsscr[1:0] transport stream serial clock rate. 00 = 80?88.5 mhz (default) 01 = 76.8?82.8 mhz 10 = 54.8?59.2 mhz 11 = 34.9?37.7 mhz the user should select a setting such that the corresponding minimum clock output frequency is higher than the expected output bit rate. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 42 preliminary rev. 0.81 register 04h. pin control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name int_en intt intp tse_oe tsv_oe tss_oe tsc_oe tsd_oe bit name function 7int_en interrupt pin enable. 0 = disabled (default) 1=enabled 6intt interrupt pin type. 0 = cmos (default) 1 = open drain/source 5intp interrupt polarity. 0 = active low (default) 1 = active high 4 tse_oe transport stream error output enable. 0=enabled 1 = tri-state (default) 3 tsv_oe transport stream valid output enable. 0=enabled 1 = tri-state (default) 2 tss_oe transport stream sync output enable. 0=enabled 1 = tri-state (default) 1tsc_oe transport stream clock output enable. 0=enabled 1 = tri-state (default) 0tsd_oe transport stream data output enable. 0=enabled 1 = tri-state (default) www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 43 register 05h. pin control 2 bitd7d6d5 d4d3d2d1d0 name 0 0 1 0 0 gpo psel[1:0] bit name function 7:3 reserved program as shown above. 2gpo general purpose output control. controls output of pin 30 when psel = 10 0 = output logic zero. (default) 1 = output logic 1. 1:0 psel[1:0] pin select (pin 30). 00 = interrupt (default) 01 = receiver lock indicator 10 = general purpose output 11 = reserved register 06h. bypass bitd7d6d5d4d3d2d1d0 name 0 0 ds_bp rs_bp di_bp 0 0 0 bit name function 7:6 reserved program as shown above. 5 ds_bp descrambler bypass. 0 = normal operation (default) 1=bypass note: this bit is ignored in dss mode; the descrambler is automatically bypassed. 4 rs_bp reed-solomon bypass. 0 = normal operation (default) 1=bypass 3di_bp deinterleaver bypass. 0 = normal operation (default) 1=bypass 2:0 reserved program as shown above. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 44 preliminary rev. 0.81 register 07h. interrupt enable 1 bit d7 d6 d5 d4 d3 d2 d1 d1 name rcvl_e agcl_e cel_e 0 stl_e crl_e vtl_e fsl_e bit name function 7 rcvl_e receiver lock interrupt enable. 0 = disabled (default) 1=enabled 6agcl_e agc lock interrupt enable. 0 = disabled (default) 1=enabled 5 cel_e carrier estimator lock interrupt enable. 0 = disabled (default) 1=enabled 4 reserved program as shown above. 3stl_e symbol timing lock interrupt enable. 0 = disabled (default) 1=enabled 2crl_e carrier recovery lock interrupt enable. 0 = disabled (default) 1=enabled 1vtl_e viterbi search lock interrupt enable. 0 = disabled (default) 1=enabled 0fsl_e frame sync lock interrupt enable. 0 = disabled (default) 1=enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 45 register 08h. interrupt enable 2 bit d7 d6 d5 d4 d3 d2 d1 d1 name rcvu_e agcts_e stu_e cru_e vtu_e fsu_e 0 aqf_e bit name function 7rcvu_e receiver unlock interrupt enable. 0 = disabled (default) 1=enabled 6agcts_e agc tracking threshold interrupt enable. 0 = disabled (default) 1=enabled 5stu_e symbol timing unlock interrupt enable. 0 = disabled (default) 1=enabled 4 cru_e carrier recovery unlo ck interrupt enable. 0 = disabled (default) 1=enabled 3vtu_e viterbi search unlock interrupt enable. 0 = disabled (default) 1=enabled 2fsu_e frame sync unlock interrupt enable. 0 = disabled (default) 1=enabled 1 reserved program as shown above. 0aqf_e acquisition fail interrupt enable. 0 = disabled (default) 1=enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 46 preliminary rev. 0.81 register 09h. interrupt enable 3 bit d7 d6 d5 d4 d3 d2 d1 d1 name cn_e vter_e rser_e msgpe_e fe_e ff_e msgr_e msgto_e bit name function 7 cn_e c/n estimator interrupt enable. 0 = disabled (default) 1=enabled 6vter_e viterbi ber interrupt enable. 0 = disabled (default) 1=enabled 5 rser_e reed-solomon error measurement interrupt enable. 0 = disabled (default) 1=enabled 4 msgpe_e lnb message parity error interrupt enable. 0 = disabled (default) 1=enabled 3fe_e lnb transmit fifo empty interrupt enable. 0 = disabled (default) 1=enabled 2 ff_e lnb receive fifo full interrupt enable. 0 = disabled (default) 1=enabled 1msgr_e lnb receive message interrupt enable. 0 = disabled (default) 1=enabled 0msgto_e lnb receive timeout interrupt enable. 0 = disabled (default) 1=enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 47 register 0ah. interrupt enable 4 bit d7 d6 d5 d4 d3 d2 d1 d0 part SI2107/8 name 0 0 0 0 0 0 scd_e ocd_e part si2109/10 name 0 bsdo_e bsda_e0 0 0 0 scd_e ocd_e bit name function 7 reserved program as shown above. 6bsdo_e blindscan done interrupt enable. 0 = disabled (default) 1 = enabled 5 bsda_e blindscan data ready interrupt enable. 0 = disabled (default) 1 = enabled 4:2 reserved program as shown above. 1 scd_e short circuit detect interrupt enable. 0 = disabled (default) 1=enabled 0ocd_e over current detect interrupt enable. 0 = disabled (default) 1=enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 48 preliminary rev. 0.81 register 0bh. interrupt status 1 bit d7 d6 d5 d4 d3 d2 d1 d1 name rcvl_i agcl_i cel_i 0 stl_i crl_i vtl_i fsl_i bit name function 7rcvl_i receiver lock interrupt. 0 = disabled (default) 1=enabled 6agcl_i agc lock interrupt. 0 = disabled (default) 1=enabled 5cel_i carrier estimator lock interrupt. 0 = disabled (default) 1=enabled 4 reserved program as shown above. 3stl_i symbol timing lock interrupt. 0 = disabled (default) 1=enabled 2 crl_i carrier recovery lock interrupt. 0 = disabled (default) 1=enabled 1vtl_i viterbi search lock interrupt. 0 = disabled (default) 1=enabled 0fsl_i frame sync lock interrupt. 0 = disabled (default) 1=enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 49 register 0ch. interrupt status 2 bitd7d6d5d4d3d2d1 d1 name rcvu_i agcts_i stu_i c ru_i vtu_i fsu_i 0 aqf_i bit name function 7 rcvu_i receiver unlock interrupt. 6agcts_i agc tracking threshold interrupt. 0 = normal operation (default) 1 = event recorded 5stu_i symbol timing unlock interrupt. 0 = normal operation (default) 1 = event recorded 4cru_i carrier recovery unlock interrupt. 0 = normal operation (default) 1 = event recorded 3vtu_i viterbi search unlock interrupt. 0 = normal operation (default) 1 = event recorded 2fsu_i frame sync unlock interrupt. 0 = normal operation (default) 1 = event recorded 1 reserved program as shown above. 0aqf_i acquisition fail interrupt. 0 = normal operation (default) 1 = event recorded www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 50 preliminary rev. 0.81 register 0dh. interrupt status 3 bit d7 d6 d5 d4 d3 d2 d1 d1 name cn_i vter_i rser_i msgpe_i fe_i ff_i msgr_i msgto_i bit name function 7cn_i c/n estimator interrupt. 0 = normal operation (default) 1 = event recorded 6vter_i viterbi ber interrupt. 0 = normal operation (default) 1 = event recorded 5rser_i reed-solomon error measurement complete interrupt. 0 = normal operation (default) 1 = event recorded 4 msgpe_i lnb message parity error interrupt. 0 = normal operation (default) 1 = event recorded 3fe_i lnb transmit fifo empty interrupt. 0 = normal operation (default) 1 = event recorded 2ff_i lnb receive fifo full interrupt. 0 = normal operation (default) 1 = event recorded 1msgr_i lnb receive message interrupt. 0 = normal operation (default) 1 = event recorded 0msgto_i lnb receive timeout interrupt. 0 = normal operation (default) 1 = event recorded www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 51 register 0eh. interrupt status 4 bit d7 d6 d5 d4 d3 d2 d1 d0 part SI2107/8 name 0 0 0 0 0 0 scd_i ocd_i part si2109/10 name 0 bsdo_i bsda_i 0 0 0 scd_i ocd_i bit name function 7 reserved program to zero. 6 bsdo_i blindscan done interrupt. 0 = normal operation (default) 1 = blindscan done over the specified frequency range 5 bsda_i blindscan data ready interrupt. 0 = normal operation (default) 1 = blindscan data can be read from registers: bs_ctf, bs_ftf, cfer, srest, bs_adcsr. 4:2 reserved program as shown above. 1scd_i short circuit detect interrupt. 0 = normal operation (default) 1 = event recorded 0ocd_i over current detect interrupt. 0 = normal operation (default) 1 = event recorded www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 52 preliminary rev. 0.81 register 0fh. lock status 1 bitd7d6d5d4d3d2d1d0 name 0 agcl cel srl stl crl vtl fsl bit name function 7 reserved program as shown above. 6agcl agc lock status. 0 = pending (default) 1=complete 5cel carrier estimation status. 0 = pending (default) 1=complete 4srl symbol rate estimation status. 0 = pending (default) 1=complete note: available on si2109/10 only. 3stl symbol timing lock status. 0 = unlocked (default) 1 = locked 2crl carrier lock status. 0 = unlocked (default) 1 = locked 1vtl viterbi lock status. 0 = unlocked (default) 1 = locked 0fsl frame sync lock status. 0 = unlocked (default) 1 = locked www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 53 register 10h. lock status 2 bit d7 d6 d5 d4 d3 d2 d1 d0 part SI2107/8 name rcvl 0 0 0 0 0 0 0 part si2109/10 name rcvl 0 0 0 0 0 bsda bsdo bit name function 7rcvl receiver lock status. 0 = unlocked (default) 1 = locked 6:2 reserved program as shown above. 1 bsda blindscan data ready (lsa stage) 0 = normal operation (default) 1 = raw carrier and symbol rate ready for readout by host. 0bsdo blindscan done. 0 = normal operation (default) 1 = blindscan sequence complete over the specified frequency range. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 54 preliminary rev. 0.81 register 11h. acquisition status bitd7d6d5d4d3d2d1d1 name aqf agcf cef srf stf crf vtf fsf bit name function 7aqf receiver acquisition status. 0 = normal operation (default) 1 = acquisition failed 6agcf agc search status. 0 = normal operation (default) 1 = gain control limit reached 5cef carrier estimation search status. 0 = normal operation (default) 1 = carrier offset not found 4srf symbol rate search status. 0 = normal operation (default) 1 = search failed note: available on si2109/10 only. 3stf symbol timing search status. 0 = normal operation (default) 1 = search failed 2 crf carrier search status. 0 = normal operation (default) 1 = search failed 1vtf viterbi search status. 0 = normal operation (default) 1 = search failed 0fsf frame sync search status. 0 = normal operation (default) 1 = search failed www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 55 register 14h. acquisition control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name aqs 0 0 0 0 0 0 0 bit name function 7aqs automatic acquisition start. writing a one to this bit initiates th e acquisition sequence. this bit is automatically cleared when the acquisition sequence completes. 6:0 reserved program as shown above. register 15h. adc sampling rate bit d7 d6 d5 d4 d3 d2 d1 d0 name adcsr[7:0] bit name function 7:0 adcsr[7:0] adc sampling rate. f s = adcsr x 1 mhz default: c8h (200 mhz) register 16h. coarse tune frequency bit d7 d6 d5 d4 d3 d2 d1 d0 name ctf[7:0] bit name function 7:0 ctf[7:0] coarse tune frequency. calculation of the coarse tune value is determined by the reference software driver. f coarse =ctfx10mhz default: 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 56 preliminary rev. 0.81 register 17h. fine tune frequency l bit d7 d6 d5 d4 d3 d2 d1 d0 name ftf[7:0] bit name function 7:0 ftf[7:0] fine tune frequency (low byte). where ftf is stored as a 2s complement value. calculation of the fine tune value is determined by the reference soft- ware driver. default: 00h register 18h. fine tune frequency h bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 ftf[14:8] bit name function 7 reserved program as shown above. 6:0 ftf[14:8] fine tune frequency (high byte). see register 17h. f fine ftf f s 2 14 -------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 57 register 1ch. host control register (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 sr_ ctrl_ host adcsr_ctrl_ host ctf_ctrl_ host ftf_ctrl_ host bit name function 7:4 reserved program as shown above. 3sr_ctrl_host symbol rate host control 0 = control by chip (during bsc) 1 = control from host (during normal operation) (default) 2 adcsr_ctrl_host adc sampling rate host control. 0 = control by chip (during bsc) 1 = control by host (during normal operation) (default) 1 ctf_ctrl_host coarse tune frequency host control. 0 = control by chip (during bsc) 1 = control by host (during normal operation) (default) 0 ftf_ctrl_host fine tune frequency host control. 0 = control by chip (during bsc) 1 = control by host (during normal operation) (default) register 23h. analog agc control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 agcw[1:0] 0 0 0 0 bit name function 7:6 reserved program as shown above. 5:4 agcw[1:0] agc measurement window. acquisition tracking 00 = 1024 (default) 65536 samples (default) 01 = 2048 131072 samples 10 = 4096 262144 samples 11 = 8192 524288 samples 3:0 reserved program as shown above. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 58 preliminary rev. 0.81 register 24h. agc control 2 bit d7 d6 d5 d4 d3 d2 d1 d0 name agctr[3:0] agco[3:0] bit name function 7:4 agctr[3:0] agc tracking threshold. specifies the maximum difference between agcpwr (28h) and agcth (27h) before making a gain adjustment. default: 1000. 3:0 agco[3:0] agc gain offset. minimum value for gain stage 4. 0000 = +0 db (default) 0001 = +1 db ? 1110 = +14 db 1111 = +15 db register 25h. analog agc 1?2 gain bitd7d6d5d4d3d2d1d0 name agc2[3:0] agc1[3:0] bit name function 7:4 agc2[3:0] analog gain stage 2 setting. default: 0h 3:0 agc1[3:0] analog gain stage 1 setting. default: 0h register 26h. analog agc 3?4 gain bitd7d6d5d4d3d2d1d0 name agc4[3:0] agc3[3:0] bit name function 7:4 agc4[3:0] analog gain stage 4 setting default: 0h 3:0 agc3[3:0] analog gain stage 3 setting default: 0h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 59 register 27h. agc threshold bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 agcth[6:0] bit name function 7 reserved program as shown above. 6:0 agcth[6:0] analog agc threshold. the value specified in this register corresponds to the desired analog agc power level. the agc loop adjust s the gain of the system to drive the agc power level to this value. default: 20h. register 28h. agc power level bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 agcpwr[6:0] bit name function 7 reserved program as shown above. 6:0 agcpwr[6:0] agc power level. represents the measured input power level after the adc in rms format. the measurement window is set by agcw. this register saturates at full scale. default: 00h. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 60 preliminary rev. 0.81 register 29h. carrier estimation control bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 1 cesr[2:0] bit name function 7:3 reserved program as shown above. 2:0 cesr[2:0] carrier estimation search range. 000 = f s /16 ( 12.0 mhz typ.) exclusive to quicklock . 001 = f s /32 ( 6.3 mhz typ.) (default) 010 = f s /64 ( 3.1 mhz typ.) 011 = f s /128 ( 1.6 mhz typ.) 100 = f s /256 ( 0.8 mhz typ.) 101 = f s /512 ( 0.4 mhz typ.) 110 = f s /1024 ( 0.2 mhz typ.) 111 = f s /2048 ( 0.1 mhz typ.) register 31h. symbol rate estimator register l (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name srest[7:0] bit name function 7:0 srest[7:0] symbol rate estimate (low byte). result of blindscan symbol rate estimator. symbol rate = srest x sampling_rate / 2^23. sampling_rate is the adc sampling ra te as calculated from bs_adcsr. default: 00h register 32h. symbol rate estimator register m (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name srest[15:8] bit name function 7:0 srest[15:8] symbol rate estimate (mid byte). see register 31h. default: 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 61 register 33h. symbol rate estimator register h (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name srest[23:16] bit name function 7:0 srest[23:16] symbol rate estimate (high byte). see register 31h. default: 00h register 36h. carrier estimator offset l bit d7 d6 d5 d4 d3 d2 d1 d0 name cfo[7:0] bit name function 7:0 cfo[7:0] carrier frequency offset (low byte). designed to store a residual carrier frequency offset for future acquisi- tions. used during carrier offset es timation to adjust the center fre- quency. note: cfo is a 16-bit two?s complement number. default: 00h search center frequency f desired cfo + f s 2 15 -------- hz = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 62 preliminary rev. 0.81 register 37h. carrier estimator offset h bit d7 d6 d5 d4 d3 d2 d1 d0 name cfo[15:8] bit name function 7:0 cfo[15:8] carrier frequency offset (high byte). see register 36h. register 38h. carrier frequency offset error l bit d7 d6 d5 d4 d3 d2 d1 d0 name cfer[7:0] bit name function 7:0 cfer[7:0] carrier frequency offset error (low byte). stores the carrier frequency offset that is identified during the carrier offset estimation stage. note: cfer is a 16-bit two?s complement number. default: 00h register 39h. carrier frequency offset error h bit d7 d6 d5 d4 d3 d2 d1 d0 name cfer[15:8] bit name function 7:0 cfer[15:8] carrier frequency offset error (high byte). see register 38h. offset cfer f s 2 15 -------- hz ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 63 register 3ah. symbol rate estimator control 2 register bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 false_alarm_proc_en bit name function 7:1 reserved program as shown above. 0 false_alarm_proc_en enable the sre to check for false symbol rate alarms default: 01h register 3fh. symbol rate l bitd7d6d5 d4d3d2d1d0 name sr[7:0] bit name function 7:0 sr[7:0] symbol rate (low byte). sampling_rate is the adc sampling rate as calculated from bs_adcsr. default: 00h. register 40h. symbol rate m bit d7 d6 d5 d4 d3 d2 d1 d0 name sr[15:8] bit name function 7:0 sr[15:8] symbol rate (mid byte). see register 3fh. symbol rate sr f s 2 24 -------- hz = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 64 preliminary rev. 0.81 register 41h. symbol rate h bit d7 d6 d5 d4 d3 d2 d1 d0 name sr[23:16] bit name function 7:0 sr[23:16] symbol rate (high byte). see register 3f. register 42h. symbol rate maximum (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name srmax[7:0] bit name function 7:0 srmax[7:0] symbol rate estimation maximum. sampling_rate is the adc sampling rate as calculated from bs_adcsr. default: 00h. register 43h. symbol rate minimum (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name srmin[7:0] bit name function 7:0 srmin[7:0] symbol rate estimation minimum. sampling_rate is the adc sampling rate as calculated from bs_adcsr. default: 00h. max symbol rate srmx f s 2 16 -------- hz = min symbol rate srmn f s 2 16 -------- hz = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 65 register 75h. digital agc 1 control bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 dagc1_en dagc1w[1:0] dagc 1t dagc1hold dagc1host 0 bit name function 7 reserved program as shown above (dev ice may change the value of this bit during operation) 6 dagc1_en enable digital agc 1 0 = disabled 1 = enabled (default) 5:4 dagc1w[1:0] digital agc measurement window 00 = 256 samples 01 = 512 samples 10 = 1024 samples (default) 11 = 2048 samples 3dagc1t select agc threshold 0 = ?15 dbfs (default) 1=?9dbfs 2 dagc1hold hold previous computed gain value on dagc1 0 = update gain after each calculation (default) 1 = do not update gain value 1 dagc1host host-controlled dagc1 enable host control of holding of gain. 0 = control internal to chip (default) 1 = host control via registers dagc1hold and dagc1t 0 reserved program as shown above. register 76h. digital agc 1 gain l bitd7d6d5d4d3d2d1d0 name dagc1[7:0] bit name function 7:0 dagc1[7:0] gain of digital agc 1 (low-byte). default: 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 66 preliminary rev. 0.81 register 77h. digital agc 1 gain h bitd7d6d5d4d3d2d1d0 name dagc1[15:8] bit name function 7:0 dagc1[15:8] gain of digital agc 1 (high-byte). default: 00h register 78h. digital agc 2 control bit d7d6d5d4d3d2 d1 d0 name reserved dagc2[3:0] dagc2w[1:0] dagc2tdis bit name function 7 reserved program as shown above. (device may change the value of this bit during operation) 6:3 dagc2[3:0] digital agc2 gain factor default: 0h 2:1 dagc2w[1:0] digital agc2 measurement window acquisition tracking 00 = 16 samples (default) 1024 samples (default) 01 = 32 samples 2048 samples 10 = 64 samples 4096 samples 11 = 128 samples 8192 samples 0dagc2tdis digital agc2 automa tic tracking disable 1 = disable automatic tracking. freeze applied to gain. 0 = enable automatic tracking. (default) register 79h. digital agc 2 threshold bitd7d6d5d4d3d2d1d0 name dagc2t[7:0] bit name function 7:0 dagc2t[7:0] digital agc2 threshold. default: b5h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 67 register 7ah. digital agc 2 level l bitd7d6d5d4d3d2d1d0 name dagc2ga[7:0] bit name function 7:0 dagc2ga[7:0] digital agc2 gain auto (low byte). digital agc2 gain applied to meet threshold default: 00h register 7bh. digital agc 2 level h bitd7d6d5d4d3d2d1d0 name dagc2ga[15:8] bit name function 7:0 dagc2ga[15:8] digital agc2 gain auto (high byte). see register 7ah. default: 00h register 7ch. c/n estimator control bitd7d6d5d4d3d2d1d0 name cns 0 0 0 0 cnm cnw[1:0] bit name function 7cns c/n estimator start. writing a one to this bit initiates an c/n estimator and clears the result stored in cnl. this bit is automatically cleared to zero when the mea- surement period elapses. 6:3 reserved program as shown above. 2cnm c/n estimator mode. 0 = finite window 1 = infinite window (default) 1:0 cnw[1:0] c/n measurement window. 00 = 1024 samples 01 = 4096 samples (default) 10 = 16384 samples 11 = 65536 samples www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 68 preliminary rev. 0.81 register 7dh. c/n estimator threshold0 bit d7 d6 d5 d4 d3 d2 d1 d0 name cnet[7:0] bit name function 7:0 cnet[7:0] c/n estimator threshold. this value defines a noise threshold for the c/n estimator. default 13h. register 7eh. c/n estimator level l bitd7d6d5 d4d3d2d1d0 name cnl[7:0] bit name function 7:0 cnl[7:0] c/n estimator level (low byte). the value in this register is to be used with an external lookup table to estimate the c/n of the input signal. default: 00h. register 7fh. c/n estimator level h bitd7d6d5 d4d3d2d1d0 name cnl[15:8] bit name function 7:0 cnl[15:8] c/n estimator level (high byte). see register 7eh. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 69 register 80h. blindscan control register bitd7d6d5 d4d3d2d1d0 name bs_start 0 bsda 0 0 0 0 coesm bit name function 7 bs_start blindscan start. 0 = normal operation (default) 1 = start blindscan. 6 reserved program as shown above. 5 bsda blindscan data ready. 0 = cleared by host. indicates host has read the valid channel information from the register bank and the device can write new values for the next channel. 1 = set by the device. remains set as long as the host has not read the channel information from the register bank. the blindscan operation waits for the host to clear the bit before writing values for the next channel. 4:1 reserved program as shown above. 0 coesm carrier offset estimation selection mode. 0 = legacy mode (default) 1= quicklock register 81h. blindscan controller minimum fr equency register l (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_fmin[7:0] bit name function 7:0 bs_fmin[7:0] lower rf frequency limit for quickscan range: default: 14h bs_fmin minimum frequency (mhz) bs_adcsr (mhz) ----------------------------------------------------------------------- - 2 14 = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 70 preliminary rev. 0.81 register 82h. blindscan controller minimum fr equency register m (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_fmin[15:8] bit name function 7:0 bs_fmin[15:8] see register 81h. default: 08h register 83h. blindscan controller minimum fr equency register h (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name 0 0 0 0 0 0 bs_fmin[17:16] bit name function 7:2 reserved program as shown above. 1:0 bs_fmin[17:16] see register 81h. default: 01h register 84h. blindscan controller maximum frequency register l (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_fmax[7:0] bit name function 7:0 bs_fmax[7:0] higher rf frequency limit for quickscan range: default: f6h bs_fmax maximum frequency (mhz) bs_adcsr (mhz) ------------------------------------------------------------------------- - 2 14 = www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 71 register 85h. blindscan controller maximum frequency register m (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_fmax[15:8] bit name function 7:0 bs_fmax[15:8] see register 84h. default: 9bh register 86h. blindscan contro ller maximum frequency register h (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name 0 0 0 0 0 0 bs_fmax[17:16] bit name function 7:2 reserved program as shown above. 1:0 bs_fmax[17:16] see register 84h. default: 02h register 89h. blindscan controller coarse tuning frequency register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_ctf[7:0] bit name function 7:0 bs_ctf[7:0] coarse frequency of id entified channel = 10 mhz x bs_ctf. default: 00h register 8ah. blindscan controller fine tuning frequency register l (si2109 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name bs_ftf[7:0] bit name function 7:0 bs_ftf[7:0] fine frequency of identified channel, low byte. fine frequency = bs_fs/16384 x bs_ftf default: 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 72 preliminary rev. 0.81 register 8bh. blindscan controller fine tuning frequency register h (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name 0 bs_ftf[14:8] bit name function 7 reserved program as shown above. 6:0 bs_ftf[14:8] fine frequency of identified channel, high byte. see register 8ah. default: 00h register 8ch. blindscan cont roller adc sampling rate regi ster (si2109 a nd si2110 only) bitd7d6d5 d4d3d2d1d0 name bs_adcsr[7:0] bit name function 7:0 bs_adcsr[7:0] blindscan adc sampling rate used for the identified channel. bs_fs = bs_adcsr x 1 mhz default: 00h register 8dh. lsa control 1 register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name 0 avg_win[6:5] 02h 01h 02h bit name function 7 reserved program as shown above. 6:5 avg_win[6:5] length of the time averaging window fo r computation for lsa in blind scan mode. refer to silicon lab oratories application note an29 8 for recommende d default val- ues for quicklock / quickscan operation. 4:3 reserved program as shown above. 2 reserved program as shown above. 1:0 reserved program as shown above. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 73 register 8eh. spectrum tilt correction threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name spec_tilt_correc[7:0] bit name function 7:0 spec_tilt_correc[7:0] correction to be applied for spectrum tilt. refer to silicon laboratories applic ation note an298 for recommended default values for quicklock / quickscan operation. register 90h. 1db bandwidth threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bw_1db bit name function 7:0 bw_1db[7:0] threshold used to determine 1 db bandwidth for a detected channel. refer to silicon laboratories applic ation note an298 for recommended default values for quicklock / quickscan operation. register 91h. 2db bandwidth threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bw_2db bit name function 7:0 bw_2db[7:0] threshold used to determine 2 db bandwidth for a detected channel. refer to silicon laboratorie s application note an298 for recommended default val- ues for quicklock / quickscan operation. register 92h. 3db bandwidth threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name bw_3db bit name function 7:0 bw_3db[7:0] threshold used to determine 3 db bandwidth for a detected channel. refer to silicon laboratories applic ation note an298 for recommended default values for quicklock / quickscan operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 74 preliminary rev. 0.81 register 93h. inband power threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name inband_threshold bit name function 7:0 inband_ threshold[7:0] threshold for determining the drop in power in a channel as the lsa scans a detected channel to determine the channel bandwidth. refer to silicon laboratorie s application note an298 fo r recommended default val- ues for quicklock / quickscan operation. register 94h. noise level margin threshold register (si2109 and si2110 only) bitd7d6d5 d4d3d2d1d0 name ref_noise_margin[7:0] bit name function 7:0 ref_noise_margin[7:0] power level thre shold for the detection of channels. refer to silicon laboratories applic ation note an298 for recommended default values for quicklock / quickscan operation. register a0h. viterbi search control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 vtcs[5:0] bit name function 7:6 reserved program as shown above. 5:0 vtcs[5:0] viterbi code rate search parameter enable. the code rates to be used in the viterbi search are selected by writing a one into the appropr iate bit position. the list below illustrates the rela- tionship between bit position and code rate. bit 5 = 7/8 code rate (msb) bit 4 = 6/7 code rate bit 3 = 5/6 code rate bit 2 = 3/4 code rate bit 1 = 2/3 code rate bit 0 = 1/2 code rate (lsb) default: all code rates selected (3fh). www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 75 register a2h. viterbi search control 2 bitd7d6d5d4d3d2d1d0 name 0 0 0 0 vters vterm vterw[1:0] bit name function 7:4 reserved program as shown above. 3vters viterbi ber measurement start writing a 1 to this bit initiates the viterbi ber measurement. 2vterm viterbi ber measurement mode 0 = finite window (default) 1 = infinite window 1:0 vterw[1:0] viterbi ber measu rement window 00 = 2 13 bits (default) 01 = 2 17 bits 10 = 2 21 bits 11 = 2 25 bits register a3h. viterbi search status bit d7 d6 d5 d4 d3 d2 d1 d0 name vtrs[2:0] 0 00 vtps vtiqs bit name function 7:5 vtrs[2:0] viterbi current code rate status. 000 = 1/2 code rate (default) 001 = 2/3 code rate 010 = 3/4 code rate 011 = 5/6 code rate 100 = 6/7 code rate 101 = 7/8 code rate 11x = undefined 4:2 reserved program as shown above. 1vtps viterbi constellation rotation phase status. 0 = not rotated (default) 1 = rotated by 90 degrees 0vtiqs viterbi i/q swap status. 0 = not swapped (default) 1 = swapped www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 76 preliminary rev. 0.81 register abh. viterbi ber count l bitd7d6d5d4d3d2d1d0 name vterc[7:0] bit name function 7:0 vterc[7:0] viterbi ber counter (low byte). stores the number of the viterbi bit errors detected within the specified measurement window. this register saturates when it reaches the limit of its range. default: 00h register ach. viterbi ber count h bitd7d6d5d4d3d2d1d0 name vterc[15:8] bit name function 7:0 vterc[15:8] viterbi ber counter (high byte). see register abh. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 77 register b0h. reed-solomon ber error monitor control bitd7d6d5d4d3d2d1d0 name 0 0 0 rsers rserm rserw rsert[1:0] bit name function 7:5 reserved program as shown above. 4 rsers reed-solomon ber measurement start. writing a 1 to this bit initiates the reed-solomon ber measurement. 3rserm reed-solomon measurement mode. 0 = finite window (default) 1 = infinite window 2 rserw reed-solomon measurement window. 0=2 12 frames (default) 1=2 16 frames 1:0 rsert[1:0] reed-solomon error type. 00 = corrected bit errors (default) 01 = corrected byte errors 10 = uncorrected packets 11 = prbs errors register b1h. reed-solomon error monitor count l bit d7 d6 d5 d4 d3 d2 d1 d0 name rserc[7:0] bit name function 7:0 rserc[7:0] reed-solomon error counter (low byte). stores the number of rs or prbs errors detected within the specified window. this register saturates when it reaches the limit of its range. default: 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 78 preliminary rev. 0.81 register b2h. reed-solomon error monitor count h bitd7d6d5d4d3d2d1d0 name rserc[15:8] bit name function 7:0 rserc[15:8] reed-solomon error counter (high byte). see register b1h. register b3h. de scrambler control bitd7d6d5d4d3d2d1d0 name 000000dst_dsdso_ds bit name function 7:2 reserved program as shown above. 1dst_ds descrambler transport e rror insertion disable. 0 = enabled (default) 1=disabled 0dso_ds descrambler inverted sync overwrite disable. 0 = enabled (default) 1=disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 79 register b5h. prbs control bit d7 d6 d5 d4 d3 d2 d1 d0 name prbs_start prbs_invert prbs_sync 0 0 0 prbs_header_size[1:0] bit name function 7 prbs_start start prbs synchronization. 1 = start prbs synchronization default = 0 6 prbs_invert invert prbs output. 1 = prbs inverted. default = 0 5 prbs_sync synchronization achieved for prbs test. 0 = not synchronized. 1 = synchronized default = 0 4:2 reserved read returns zero. 1:0 prbs_header_size packet header size. this signals the number of bytes at the start of a ts packet that are con- sidered ts header, and that are not occupied by prbs data in prbs test mode. dvb-s mode dss mode 00 = 1 0 (default) 01 = 2 1 10 = 3 2 11 = 4 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 80 preliminary rev. 0.81 register c0h. lnb control 1 bit d7 d6 d5 d4 d3 d2 d1 d0 part SI2107/9 name lnbs 0 lnbct lnbb mmsg msgl[2:0] part si2108/10 name lnbs lnbv lnbct lnbb mmsg msgl[2:0] bit name function 7lnbs lnb start. writing a 1 to this bit initiates an lnb si gnaling sequence. this bit is automatically cleared to zero when the sequence is complete. note: not available in manual lnb mode. 6lnbv lnb dc voltage selection. 0 = 13 v (default) 1=18v 5 lnbct continuous tone selection. 0 = normal operation (default) 1 = send continuous tone note: not available in manual lnb mode. 4lnbb tone burst selection. 0 = unmodulated tone burst (default) 1 = modulated tone burst note: for use in automatic lnb mode only. use a 1-byte diseqc message for tone burst implementation in step-by-step lnb mode. 3mmsg more messages. 0 = normal operation (default) 1 = indicates more diseqc messages to be sent this bit is automatically cleared to zero when the sequence is complete. note: for use in automatic lnb mode only. 2:0 msgl[2:0] message length. 000 = no message (default) 001 = one byte 010 = two bytes 011 = three bytes 100 = four bytes 101 = five bytes 110 = six bytes 111 = longer than six bytes. notes: 1. when message length is set to one byte, tone burst modulation is used. when message length is set to two or more bytes, diseqc modulation is used. 2. not available in manual lnb mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 81 register c1h. lnb control 2 bitd7d6d5 d4d3 d2 d1d0 name lnbm[1:0] 0 0 0 brst_ds tfs 0 bit name function 7:6 lnbm[1:0] lnb signaling mode. 00 = automatic (default) 01 = step-by-step 10 = manual 11 = reserved 5:3 reserved program as shown above. 2 brst_ds tone burst disable. 0 = enabled (default) 1 = disabled note: for use in automatic lnb mode only, in conjunction with lnbb (c0h[4]) 1tfs tone format select. 0 = tone generation/detection (default) 1 = envelope generation/detection 0 reserved program as shown above. register c2h. lnb control 3 bitd7d6d5d4 d3 d2 d1 d0 name tdir tt tr 0 0 0 0 0 bit name function 7tdir tone direction control. controls output of drc pin. 0 = low (logic zero) (default) 1 = high (logic one) note: this bit is only active in manual lnb mode. 6tt tone transmit. controls output of tgen pin. 0 = tone off / low (logic zero) (default) 1 = tone on / high (logic one) note: this bit is only active in manual lnb mode. 5tr tone receive. detects input on tdet pin. 0 = no tone or low signal detected (default) 1 = tone or high signal detected note: this bit is only active in manual lnb mode. 4:0 reserved program as shown above. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 82 preliminary rev. 0.81 register c3h. lnb control 4 bitd7d6d5d4d3d2d1d1 name tfq[7:0] bit name function 7 tfq[7:0] lnb tone frequency control. used to set the frequency of the lnb tone according to the following equation: frequency = 100 mhz/[32 x (tfq+1)] 00000000?01111011 = reserved 01111100?10011011 = valid range 10011100?11111111 = reserved default: 8dh = 22 khz www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 83 register c4h. lnb status bitd7d6d5d4d3d2d1d0 name fe ff msgpe msgr msgto msgrl[2:0] bit name function 7fe message fifo empty. 0 = normal operation (default) 1 = message fifo empty 6ff message fifo full. 0 = normal operation (default) 1 = message fifo full 5 msgpe message parity error. 0 = normal operation (default) 1 = parity error detected 4msgr message received. 0 = normal operation (default) 1 = message received 3msgto message timeout. 0 = normal operation (default) 1 = message reply not received within 150 ms 2:0 msgrl[2:0] received message length. 000 = no message (default) 001 = one byte 010 = two bytes 011 = three bytes 100 = four bytes 101 = five bytes 110 = six bytes 111 = longer than six bytes www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 84 preliminary rev. 0.81 register c5-cah. message fifo 1?6 bit d7 d6 d5 d4 d3 d2 d1 d0 name fif0x[7:0] bit name function 7:0 fifo1?6[7:0] message fifo. contains message to be transmitted or message received register cbh. lnb supply control 1 (si2108 and si2110 only) bit d7 d6 d5 d4 d3 d2 d1 d0 name vlow[3:0] vhigh[3:0] bit name function 7:4 vlow[3:0] lnb supply low voltage. low voltage = vlow_nom + vlow[3:0] x 0.0625v + vboost, where vlow_nom is determined by the lnbv( c0h[6]) register bit, and vboost is determined by the comp(ceh[2]) register bit. default: low voltage = vlow_nom + 0.0 v + vboost. 3:0 vhigh[3:0] lnb supply high voltage. high voltage = vhigh_nom + vhigh[3:0] x 0.0625v + vboost, where vhigh_nom is determined by the lnbv(c0h[6]) register bit, and vboost is determined by the comp(ceh[2]) register bit. default: high voltage = vhigh_nom + 0.0 v + vboost. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 85 register cch. lnb supply control 2 (si2108 and si2110 only) bitd7d6d5d4d3d2d1d0 name ilim[1:0] imax[1:0] slot[1:0] olot[1:0] bit name function 7:6 ilim[1:0] average current limit. 00 = 400 ? 550 ma (default) 01 = 500 ? 650 ma 10 = 650 ? 850 ma 11 = 800 ? 1000 ma 5:4 imax[1:0] peak current limit. 00 = 1.2 a (default) 01 = 1.6 a 10 = 2.4 a 11 = 3.2 a 3:2 slot[1:0] short circuit lockout time. 00 = 15 s initial; 240 s secondary 01 = 20 s initial; 320 s secondary (default) 10 = 40 s initial; 480 s secondary 11 = 20 s 1:0 olot[1:0] overcurrent lockout time. 00 = 2.5 ms 01 = 3.75 ms 10 = 5.0 ms (default) 11 = 7.5 ms note: this register byte is read-only if lnbl=1. register cdh. lnb supply control 3 (si2108 and si2110 only) bitd7d6d5d4d3d2d1d0 name vmon[7:0] bit name function 7:0 vmon[7:0] lnb voltage monitor (read only). lnb output voltage = vmon x 0.0625 + 6 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 86 preliminary rev. 0.81 register ceh. lnb supply control 4 (si2108 and si2110 only) bitd7d6d5d4 d3 d2d1d0 name lnbl 0 0 0 lnb_en comp 0 lnbmd bit name function 7lnbl lnb supply lock. writing a one to this bit locks the contents of register cch. this bit can only be cleared by a device reset. 6:4 reserved program as shown above. 3lnb_en lnb supply enable. 0 = disabled (default) 1=enabled 2comp lnb cable compensation boost. 0 = normal operation (default) 1 = lnb output voltage increased +1 v 1 reserved program as shown above. 0lnbmd lnb mode detect. detected supply mode (read-only) 0 = external lnb supply circuit 1 = internal lnb supply circuit register cfh. lnb supply status (si2108 and si2110 only) bitd7d6d5d4d3d2d1d0 name 000000scdocd bit name function 7:2 reserved program as shown above. 1scd short-circuit detect flag. 0 = normal operation (default) 1 = short-circuit detected 0ocd overcurrent detect flag. 0 = normal operation (default) 1 = overcurrent detected. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 87 9. pin descriptions si2108/10 SI2107/09 pin # name i/o description 1vdd_lnai supply voltage. lna power supply. connect to 3.3 v. 2 rext i external reference resistor. connect 4.53 k ? to gnd. 3 addr i i 2 c address select. 4vdd_mixi supply voltage. mixer power supply. connect to 3.3 v 5vdd_bbi supply voltage. baseband power supply. connect to 1.8 v. 6 vdd_adc i supply voltage. adc power supply. connect to 3.3 v. 7 vsen/tdet i voltage sense/tone detect. vsen (si2108/10 only)?line volt age of lnb supply circuit. tdet?detect input of external tone or tone envelope. 8 lnb1/tgen o lnb control 1/tone generation. lnb1 (si2108/10 only)?required connection to lnb supply circuit. tgen?outputs tone or tone envelope. 9iseni current sense (si2108/10 only). monitors current of lnb supply circuit. when lnb supply circuit is not populated or when using SI2107/09, leave pin unconnected. 10 lnb2/drc o lnb control 2/direction control. lnb2 (si2108/10 only)?required connection to lnb supply circuit. drc?outputs signal to indicate message transmission (hig h) or reception (low). 11 reset i device reset. active low. 14 15 16 17 18 19 20 21 22 36 37 38 39 40 41 42 43 44 vdd_synth vdd_lo gnd rfip1 rfin1 rfin2 rfip2 vdd_lna rext addr vdd_mix vdd_bb vdd_adc vsen/tdet lnb1/tgen isen pwm/dcs vdd_dig18 ts_data[1] ts_data[7] ts_clk scl sda ts_sync ts_val ts_err int/rlk/gpo vdd_pll33 xtout vdd_xtal xtal2 xtal1 reset lnb2/drc ts_data[0] ts_data[3] ts_data[2] ts_data[4] ts_data[5] ts_data[6] vdd_dig33 vdd_dig33 gnd gnd top view 1 2 3 4 5 6 7 8 9 10 11 12 13 23 24 25 26 27 28 29 30 31 32 33 34 35 gnd gnd 14 15 16 17 18 19 20 21 22 36 37 38 39 40 41 42 43 44 vdd_synth vdd_lo gnd rfip1 rfin1 rfin2 rfip2 vdd_lna rext addr vdd_mix vdd_bb vdd_adc tdet tgen nc dcs vdd_dig18 ts_data[1] ts_data[7] ts_clk scl sda ts_sync ts_val ts_err int/rlk/gpo vdd_pll33 xtout vdd_xtal xtal2 xtal1 reset drc ts_data[0] ts_data[3] ts_data[2] ts_data[4] ts_data[5] ts_data[6] vdd_dig33 vdd_dig33 gnd gnd top view 1 2 3 4 5 6 7 8 9 10 11 12 13 23 24 25 26 27 28 29 30 31 32 33 34 35 gnd gnd www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 88 preliminary rev. 0.81 12 pwm/dcs o pwm/dc voltage select. pwm (si2108/10 only)?connected to gate of power mosfet for lnb supply cir- cuit. dcs?outputs signal to indicate 18 v (high) or 13 v (low) lnb supply voltage selection. 13 vdd_dig18 i supply voltage. digital power supply. connect to 1.8 v. 14?17, 21?24 ts_data[7:0] o transport stream data bus. serial data is output on ts_data[0]. 18, 20 vdd_dig33 i supply voltage. digital power supply. connect to 3.3 v. 19 ts_clk o transport stream clock. 25 scl i i 2 c clock. 26 sda i/o i 2 c data. 27 ts_sync o transport stream sync. 28 ts_val o transport stream valid. 29 ts_err o transport stream error. 30 int/rlk/ gpo o multi purpose output pin. this pin can be configured to one of the following outputs using the pin ctrl 2 (05h) register. int = interrupt rlk = receiver lock indicator gpo = general purpose output 31 vdd_pll33 i supply voltage. analog pll power supply. connect to 3.3 v. 32 xtout o no connect/crystal oscillator output. if this device is to be used as the clock master in a multi-channel design, this pin should be connect to the xtal1 pin of a clock slave device. (otherwise, this pin should be left unconnected.) 33 vdd_xtal i supply voltage. crystal oscillator power supply. connect to 3.3 v. 34 xtal2 o crystal oscillator. connect to 20 mhz crystal unit. 35 xtal1 i crystal oscillator. connect to 20 mhz crystal unit. 36 vdd_synth i supply voltage. synth power supply. connect to 3.3 v. 37 vdd_lo i supply voltage. local oscillator power supply. connect to 3.3 v. 38,41,44 gnd i ground. reference ground. 39, 43 rfip1, rfip2 i rf input. these pins must be connected together on the board. 40, 42 rfin1, rfin2 i rf input. these pins must be connected together on the board. epad gnd i ground. reference ground. pin # name i/o description www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 89 10. ordering guide 1,2 ordering part # description temperature si2110-x-fm satellite receiver for dvb-s/dss with lnb step-up dc-dc controller and on-chip blindscan accelerator, pb-free and rohs compliant 0 to 70 c si2109-x-fm satellite receiver for dvb-s/dss with on-chip blindscan accelerator, pb-free and rohs compliant 0 to 70 c si2108-x-fm satellite receiver for dvb-s/ dss with step-up dc-dc controller, pb- free and rohs compliant 0 to 70 c SI2107-x-fm satellite receiver for dvb-s/ dss, pb-free and rohs compliant 0 to 70 c notes: 1. ?x? denotes product revision. 2. add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 90 preliminary rev. 0.81 11. package outline: 44-pin qfn figure 23 illustrates the packag e details for the si2110. table 20 lists the values for the dimensions shown in the illustration. figure 23. 44-pin qfn table 20. package diagram dimensions dimension millimeters dimension millimeters min nom max min nom max a 0.80 0.90 1.00 e2 6.00 6.10 6.20 a1 0.00 0.02 0.05 l 0.45 0.55 0.65 b 0.18 0.25 0.30 l1 0.03 0.05 0.08 d 6.00 bsc. aaa 0.10 d2 2.70 2.80 2.90 bbb 0.10 e 0.50 bsc. ccc 0.08 e 8.00 bsc. ddd 0.10 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. this drawing conforms to the jedec solid state outline mo-220, variation vjld. 3. recommended card reflow profile is per the jedec/ip c j-std-020c specification for small body components. 4. the pin 1 i.d. pad is for component orientation only and is not to be soldered to the pcb. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 91 12. pcb land pattern figure 24. pcb land pattern www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 92 preliminary rev. 0.81 table 21. pcb land pattern dimensions dimension min max e0.50 bsc e7.51 ref d5.51 ref e2 6.00 6.20 d2 2.70 2.90 ge 6.71 -- gd 4.71 -- x ? 0.28 y0.80 ref ze ? 8.31 zd ? 6.31 notes - general: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximu m material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes - solder mask design: 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes - stencil design: 1. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 3x6 array of 0.70mm square openings on 0.95mm pitch should be used for the center ground pad. notes - card assembly: 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 preliminary rev. 0.81 93 d ocument c hange l ist revision 0.4 to revision 0.5 package dimensions changed to 6 x 8 mm. updated pin numbering and pin descriptions. schematics updated. i 2 c interface description added. mpeg-ts timing specifications added. revision 0.5 to revision 0.6 data sheet for SI2107/08/09/10. added detailed operational description. register map changed for rev. c silicon. various editorial changes and corrections. revision 0.6 to revision 0.7 updated application diagram and bom. added table for multi-device i 2 c address support. revision 0.7 to revision 0.8 added detailed operational description of quickscan functionality in "6.9. on-c hip blindscan controller: quickscan (si2109/10 only)" on page 32. added graphs of perform ance illustrating typical performance. figure 4, ?eb/no (qef operation) vs. input power for SI2107/08/09/10 (typical) sr = 27.5 mbaud, cr = 7/8,? on page 11. figure 5, ?ber after viterbi vs. eb/no for SI2107/08/09/ 10,? on page 11. figure 6, ?phase noise performance for SI2107/08/09/ 10 (typical),? on page 12. updated ?2. typical a pplication schematics?. figure 8, ?SI2107/08/09/10 schematic,? on page 13 figure 9, ?diseqc 1.x lnb supply circuit,? on page 14 figure 10, ?diseqc 2.x lnb supply circuit,? on page 15. updated "3. bill of ma terials" on page 16. added "12. pcb land pattern" on page 91. revision 0.8 to revision 0.81 updated documentation on quicklock and quickscan details. added figure 7, ?frequency offset vs. carrier lock/ acquisition time for various baudrates using quicklock (typical),? on page 12. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SI2107/08/09/10 94 preliminary rev. 0.81 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: dbsinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. www.datasheet.net/ datasheet pdf - http://www..co.kr/

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